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charset=UTF-8 Date: Tue, 22 Apr 2025 22:06:00 +0900 Message-Id: To: "Danilo Krummrich" , "Joel Fernandes" Cc: "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Jonathan Corbet" , "John Hubbard" , "Ben Skeggs" , "Timur Tabi" , "Alistair Popple" , , , , Subject: Re: [PATCH 08/16] gpu: nova-core: wait for GFW_BOOT completion From: "Alexandre Courbot" X-Mailer: aerc 0.20.1-0-g2ecb8770224a References: <20250420-nova-frts-v1-0-ecd1cca23963@nvidia.com> <20250420-nova-frts-v1-8-ecd1cca23963@nvidia.com> <64d869aa-587f-49c6-8626-d2085441bb3b@nvidia.com> In-Reply-To: X-ClientProxiedBy: TY2PR0101CA0041.apcprd01.prod.exchangelabs.com (2603:1096:404:8000::27) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|SA1PR12MB5660:EE_ X-MS-Office365-Filtering-Correlation-Id: 94127901-35b2-4a3d-bfb2-08dd819e6f6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|10070799003|1800799024|366016; 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Methods for device initialization. >>=20 >> Let us clarify what devinit means. >>=20 >> devinit is a sequence of register read/writes after reset that performs = tasks >> such as: >> 1. Programming VRAM memory controller timings. >> 2. Power sequencing. >> 3. Clock and PLL configuration. >> 4. Thermal management. >> 5. Performs VRAM memory scrubbing (ECC initialization) - on some GPUs, i= t scrubs >> only part of memory and then kicks of 'async scrubbing'. >>=20 >> devinit itself is a 'script' which is interpreted by the PMU microcontro= ller of >> of the GPU by an interpreter program. >>=20 >> Note that devinit also needs to run during suspend/resume at runtime. > > Thanks for writing this up. I fully agree that those things have to be > documented. > >>=20 >> I talked with Alex and I could add a new patch on top of this patch to a= dd these >> clarifying 'doc' comments as well. I will commit them to my git branch a= nd send >> on top of this as needed, but Alex can feel free to decide to squash the= m as well. > > Fine with both, whatever you guys prefer. If that works with you, I will put Joel's patches improving the documentation right after mines adding the code in the next revision. I know this ideally should be a single patch, but researching this stuff (and producing a proper writeup) is quite involved and a separate kind of task from the quickly-translate-code-while-peeking-at-OpenRM work that I did.=20 > >>=20 >> > + >> > +use kernel::bindings; >> > +use kernel::devres::Devres; >> > +use kernel::prelude::*; >> > + >> > +use crate::driver::Bar0; >> > +use crate::regs; >> > + >> > +/// Wait for devinit FW completion. >> > +/// >> > +/// Upon reset, the GPU runs some firmware code to setup its core par= ameters. Most of the GPU is >> > +/// considered unusable until this step is completed, so it must be w= aited on very early during >> > +/// driver initialization. >> > +pub(crate) fn wait_gfw_boot_completion(bar: &Devres) -> Result<= ()> { >>=20 >> To reduce acronym soup, we can clarify gfw means 'GPU firmware', it is a= broad >> term used for VBIOS ROM components several of which execute before the d= river >> loads. Perhaps that part of comment can be 'the GPU firmware (gfw) code'= . > > Yes, we should absolutely explain acronyms as well as use consistent and = defined > terminology when referring to things. > > I think we should put both into Documentation/gpu/nova/ and add the > corresponding pointers in the code. SGTM. > >> I find this Rust convention for camel casing long constants very unreada= ble and >> troubling: Pgc6AonSecureScratchGroup05. I think we should relax this req= uirement >> for sake of readability. Could the Rust community / maintainers provide = some input? >>=20 >> Apart from readability, it also makes searching for the same register na= me a >> nightmare with other code bases written in C. >>=20 >> Couple of ideas discussed: >>=20 >> 1. May be have a macro that converts >> REG(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK) -> >> regs::Pgc6AonSecureScratchGroup05 ? >> But not sure what it takes on the rust side to implement a macro like th= at. >>=20 >> 2. Adding doc comments both in regs.rs during defining the register, and >> possibly at the caller site. This still does address the issue fully. > > If that addresses your concern, it sounds totally reasonable to me. Sorry, I'm having trouble understanding what you guys are agreeing on. :) The most radical option would be to define the registers directly as capital snake-case (NV_PGC6_...), basically a 1:1 match with OpenRM. This would be the easiest way to cross-reference, but goes against the Rust naming conventions. If we go all the way, this also means the field accessors would be capital snake-case, unless we figure out a smart macro to work this around...