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charset=UTF-8 Date: Wed, 23 Apr 2025 22:03:30 +0900 Message-Id: Cc: "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Jonathan Corbet" , "John Hubbard" , "Ben Skeggs" , "Joel Fernandes" , "Timur Tabi" , "Alistair Popple" , , , , Subject: Re: [PATCH 09/16] gpu: nova-core: register sysmem flush page From: "Alexandre Courbot" To: "Danilo Krummrich" X-Mailer: aerc 0.20.1-0-g2ecb8770224a References: <20250420-nova-frts-v1-0-ecd1cca23963@nvidia.com> <20250420-nova-frts-v1-9-ecd1cca23963@nvidia.com> In-Reply-To: X-ClientProxiedBy: TYCP286CA0056.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b5::17) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB7947:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c5ecee3-9a27-4327-872d-08dd8267405d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|10070799003|1800799024|7416014|376014; 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Do this early as it >> can be required to e.g. reset the GPU falcons. >>=20 >> Signed-off-by: Alexandre Courbot >> --- >> drivers/gpu/nova-core/dma.rs | 54 +++++++++++++++++++++++++++++++= +++++++ >> drivers/gpu/nova-core/gpu.rs | 53 +++++++++++++++++++++++++++++++= ++++-- >> drivers/gpu/nova-core/nova_core.rs | 1 + >> drivers/gpu/nova-core/regs.rs | 10 +++++++ >> 4 files changed, 116 insertions(+), 2 deletions(-) >>=20 >> diff --git a/drivers/gpu/nova-core/dma.rs b/drivers/gpu/nova-core/dma.rs >> new file mode 100644 >> index 0000000000000000000000000000000000000000..a4162bff597132a04e002b2b= 910a4537bbabc287 >> --- /dev/null >> +++ b/drivers/gpu/nova-core/dma.rs >> @@ -0,0 +1,54 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> + >> +//! Simple DMA object wrapper. >> + >> +// To be removed when all code is used. >> +#![allow(dead_code)] >> + >> +use kernel::device; >> +use kernel::dma::CoherentAllocation; >> +use kernel::page::PAGE_SIZE; >> +use kernel::prelude::*; >> + >> +pub(crate) struct DmaObject { >> + pub dma: CoherentAllocation, >> + pub len: usize, > > This should be covered by CoherentAllocation already, no? If it does not = have a > public accessor for its size, please add it for CoherentAllocation instea= d. I > can take the corresponding patch through the nova tree. `CoherentAllocation::count` is currently not accessible publicly. I agree that exposing it would make sense, let me add a patch doing that. > >> + #[allow(dead_code)] > > Please prefer #[expect(dead_code)], such that we are forced to remove it = once > it's subsequently used. Ah, that's indeed more suitable, thanks! > >> + pub name: &'static str, >> +} >> + >> +impl DmaObject { >> + pub(crate) fn new( >> + dev: &device::Device, >> + len: usize, >> + name: &'static str, >> + ) -> Result { >> + let len =3D core::alloc::Layout::from_size_align(len, PAGE_SIZE= ) >> + .map_err(|_| EINVAL)? >> + .pad_to_align() >> + .size(); >> + let dma =3D CoherentAllocation::alloc_coherent(dev, len, GFP_KE= RNEL | __GFP_ZERO)?; >> + >> + Ok(Self { dma, len, name }) >> + } >> + >> + pub(crate) fn from_data( >> + dev: &device::Device, >> + data: &[u8], >> + name: &'static str, >> + ) -> Result { >> + Self::new(dev, data.len(), name).and_then(|mut dma_obj| { >> + // SAFETY: >> + // - The copied data fits within the size of the allocated = object. >> + // - We have just created this object and there is no other= user at this stage. >> + unsafe { >> + core::ptr::copy_nonoverlapping( >> + data.as_ptr(), >> + dma_obj.dma.start_ptr_mut(), >> + data.len(), >> + ); >> + } >> + Ok(dma_obj) >> + }) >> + } >> +} > > The DMA wrapper should probably be added in a separate patch. Sure. > >> diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs >> index 1f7799692a0ab042f2540e01414f5ca347ae9ecc..d43e710cc983d51f053dacbd= 77cbbfb79fa882c3 100644 >> --- a/drivers/gpu/nova-core/gpu.rs >> +++ b/drivers/gpu/nova-core/gpu.rs >> @@ -3,6 +3,7 @@ >> use kernel::{device, devres::Devres, error::code::*, pci, prelude::*}; >> =20 >> use crate::devinit; >> +use crate::dma::DmaObject; >> use crate::driver::Bar0; >> use crate::firmware::Firmware; >> use crate::regs; >> @@ -145,12 +146,30 @@ fn new(bar: &Devres) -> Result { >> } >> =20 >> /// Structure holding the resources required to operate the GPU. >> -#[pin_data] >> +#[pin_data(PinnedDrop)] >> pub(crate) struct Gpu { >> spec: Spec, >> /// MMIO mapping of PCI BAR 0 >> bar: Devres, >> fw: Firmware, >> + sysmem_flush: DmaObject, > > Please add a doc-comment for this DmaObject explaining what it is used fo= r by > the driver and why it is needed. Will do. > >> +} >> + >> +#[pinned_drop] >> +impl PinnedDrop for Gpu { >> + fn drop(self: Pin<&mut Self>) { >> + // Unregister the sysmem flush page before we release it. >> + let _ =3D with_bar!(&self.bar, |b| { >> + regs::PfbNisoFlushSysmemAddr::default() >> + .set_adr_39_08(0) >> + .write(b); >> + if self.spec.chipset >=3D Chipset::GA102 { >> + regs::PfbNisoFlushSysmemAddrHi::default() >> + .set_adr_63_40(0) >> + .write(b); >> + } >> + }); >> + } >> } >> =20 >> impl Gpu { >> @@ -173,6 +192,36 @@ pub(crate) fn new( >> devinit::wait_gfw_boot_completion(&bar) >> .inspect_err(|_| pr_err!("GFW boot did not complete"))?; >> =20 >> - Ok(pin_init!(Self { spec, bar, fw })) >> + // System memory page required for sysmembar to properly flush = into system memory. >> + let sysmem_flush =3D { >> + let page =3D DmaObject::new( >> + pdev.as_ref(), >> + kernel::bindings::PAGE_SIZE, >> + "sysmem flush page", >> + )?; >> + >> + // Register the sysmem flush page. >> + with_bar!(bar, |b| { >> + let handle =3D page.dma.dma_handle(); >> + >> + regs::PfbNisoFlushSysmemAddr::default() >> + .set_adr_39_08((handle >> 8) as u32) >> + .write(b); >> + if spec.chipset >=3D Chipset::GA102 { >> + regs::PfbNisoFlushSysmemAddrHi::default() >> + .set_adr_63_40((handle >> 40) as u32) >> + .write(b); >> + } >> + })?; >> + >> + page >> + }; >> + >> + Ok(pin_init!(Self { >> + spec, >> + bar, >> + fw, >> + sysmem_flush, >> + })) >> } >> } >> diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/= nova_core.rs >> index 878161e060f54da7738c656f6098936a62dcaa93..37c7eb0ea7a926bee4e3c661= 028847291bf07fa2 100644 >> --- a/drivers/gpu/nova-core/nova_core.rs >> +++ b/drivers/gpu/nova-core/nova_core.rs >> @@ -21,6 +21,7 @@ macro_rules! with_bar { >> } >> =20 >> mod devinit; >> +mod dma; >> mod driver; >> mod firmware; >> mod gpu; >> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.= rs >> index fd7096f0ddd4af90114dd1119d9715d2cd3aa2ac..1e24787c4b5f432ac25fe399= c8cb38b7350e44ae 100644 >> --- a/drivers/gpu/nova-core/regs.rs >> +++ b/drivers/gpu/nova-core/regs.rs >> @@ -14,6 +14,16 @@ >> 28:20 chipset =3D> try_into Chipset, "chipset model" >> ); >> =20 >> +/* PFB */ >> + >> +register!(PfbNisoFlushSysmemAddr@0x00100c10; >> + 31:0 adr_39_08 =3D> as u32 >> +); >> + >> +register!(PfbNisoFlushSysmemAddrHi@0x00100c40; >> + 23:0 adr_63_40 =3D> as u32 >> +); > > Please add some documentation for the register and its fields. Ack. Thanks, Alex.