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Thu, 08 May 2025 06:31:08 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 08 May 2025 15:31:07 +0200 Message-Id: Subject: Re: [PATCH 1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit Cc: , , , , "linux-riscv" To: "Atish Patra" , "Anup Patel" , "Atish Patra" , "Paul Walmsley" , "Palmer Dabbelt" , "Alexandre Ghiti" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com> In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com> 2025-05-05T14:39:26-07:00, Atish Patra : > Currently, we enable the smstateen bit at vcpu configure time by > only checking the presence of required ISA extensions. > > These bits are not required to be enabled if the guest never uses > the corresponding architectural state. Enable the smstaeen bits > at runtime lazily upon first access. What is the advantage of enabling them lazily? To make the trap useful, we would have to lazily perform initialization of the AIA. I think it would require notable changes to AIA, though... Thanks.