From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 016781D6188; Thu, 28 Aug 2025 19:57:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756411041; cv=none; b=rd7W/j4bcjkzbtGfmK5Hxbua1BpxaIfxUtM3+/XhLos//vAgVQLEYzQ0ZLAVithjn4OjfeSQXcK5FTXJEUEFajG2f3oTqCvazvlrM6azJ9AKWx8ojKRn6ICSuisjcmOXIwhCanCpHKVQMrmamw1AYz3zCh/ZzYqyPBgxPR/N9Kg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756411041; c=relaxed/simple; bh=J9p1+SFkJ1DD0HNbdzfpG7QiXzTQqNC+170Di7UX3P8=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:Cc:To:From: References:In-Reply-To; b=tbPqo8wVaD25LKwPHo9pbFhrPDOqk9Cnu6D3I0lK1zudAVzyUWcBJnJg6NSFDr0HdTeypRQeTkctp66amMyjyp1ihDBQNAeR8/sOOhVOtGQuKkn2RBMYy11iv6I0DtnFC9o88tZObsgBloeuhqM8C4P6yknCqE3YGUl0tSVsR0U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kNzv9GTB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kNzv9GTB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AFA52C4CEEB; Thu, 28 Aug 2025 19:57:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756411040; bh=J9p1+SFkJ1DD0HNbdzfpG7QiXzTQqNC+170Di7UX3P8=; h=Date:Subject:Cc:To:From:References:In-Reply-To:From; b=kNzv9GTBNQw2jmLbuHmLZwNm2lSRbeCVYQ8MZyO7IT4qf+br2F68+vMxaR6PNdrzP 1X8X0YEiamcGhGG5GXHBcCW2ncGrs7CQPvsiFVeqoty2ZhrZWX6KKUqTb1euHHcpFK hvNF9FUDlhjdu6iXqa9yuH3uvKsCEtzjc6vevSa33siMTlemYmawxKt9LWn88KvvST I/UmSsYXKQ0d3l3m9a00ZXevKDezOezVyGqdrNfZ+QsbxdznbjMk4PejknKbcxmI6g c5/Sn98//btbhZVl+z/Mn6tPawLn61Rp78bs0COCJhcQuX/9Bciwn3q+DOYVwvDRPM ZuEU5ofQTpT/g== Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 28 Aug 2025 21:57:16 +0200 Message-Id: Subject: Re: gpu: nova-core: arm32 build errors Cc: "Miguel Ojeda" , "Alexandre Courbot" , "David Airlie" , "Simona Vetter" , , , , To: "Miguel Ojeda" From: "Danilo Krummrich" References: <20250828160247.37492-1-ojeda@kernel.org> In-Reply-To: On Thu Aug 28, 2025 at 9:31 PM CEST, Miguel Ojeda wrote: > On Thu, Aug 28, 2025 at 9:24=E2=80=AFPM Danilo Krummrich wrote: >> >> Maybe I spoke too soon, it's actually pretty painful to keep 32-bit >> compatibility, even though it would be nice for testing purposes. >> >> I'll paste the diff to fix it below, I think that makes it obvious why I= say >> that. >> >> Instead, we should really just depend on CONFIG_64BIT (which implies >> ARCH_DMA_ADDR_T_64BIT). > > Yeah, it isn't great. > > If it were just that, maybe it it is worth it (and a `DmaAddress` > newtype, not just a typedef, could perhaps be nice anyway?) What do you have in mind what the newtype can do? I assume the idea is to make it provide methods {to,from}_u64, where to_u64= () has to be fallible? This would be an improvement, but not really solve the = issue entirely. The annoying part really is pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> DmaAddress { let addr =3D u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).= adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT | u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_= 63_40()) << FLUSH_SYSMEM_ADDR_SHIFT_HI; =09 addr.try_into().unwrap_or_else(|_| { kernel::warn_on!(true); =09 0 }) } i.e. when we read a u64 from registers, but we know that what we've orignal= ly written there is a DmaAddress, so we can assume that a cast to DmaAddress i= s fine. But this really depends on driver specific semantics. > but if > you think it will become increasingly painful later, then it may be > best to focus on what matters. We'll have a couple more such cases for sure; I think being able to assume = that DmaAddress is always 64-bit will result in simpler and less distracting cod= e. But if we can come up with a good idea to deal with this with a DmaAddress = type; I'm open to that. > It is unlikely there is going to be actual users on a 32-bit platform, ri= ght? Yeah, I doubt that someone could think it's a great idea to run a Turing+ G= PU on some 32-bit machine.