Re: [PATCH RFC v2 1/4] dt-bindings: clk: zte: Add zx297520v3 clock and reset bindings.

["Stefan Dösinger" <stefandoesinger@gmail.com>]

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Hi Conor,

Thanks for your reply!

> Am 11.05.2026 um 19:07 schrieb Conor Dooley <conor@kernel.org>:
> 
> How come the "matrixclk" has no constraints on clock properties?

Because I am not sure what the correct/preferred way to express the interface between top and matrix is - see the first question raised in my cover letter.

In short, matrix potentially consumes all clocks available on the top controller. There is no obvious interface between them, like there is between matrix and LSP. So I see two ways to handle this in the bindings:

1) List the top clk inputs, top clk PLL outputs and PLL fractionals as matrix input
2) Be quiet about it

It'd be about 20 clocks or so that I know are consumed. The bigger issue than the number of clocks is that my knowledge of the board is from reverse engineering, not proper datasheets, so I might find out that a clock is missing or wrong.

> Although, these two devices seem too different to be in the same
> dt-binding. Do they have anyhting in common other than the SoC they are
> part of?

No, they don't have anything in common, other than that their concerns are poorly separated in hardware.

I take it from your question that the preferred way is to have separate bindings for them in this case - I guess separate headers as well as separate yaml files. Is this correct?

The third clock controller - LSP - is nicely separated from the other two. I would not be surprised to see this subsystem of the board show up on a different ZTE board. If top and matrix should have different bindings, LSP certainly should as well.

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