From: "Danilo Krummrich" <dakr@kernel.org>
To: "Zhi Wang" <zhiw@nvidia.com>
Cc: <rust-for-linux@vger.kernel.org>, <bhelgaas@google.com>,
<kwilczynski@kernel.org>, <ojeda@kernel.org>,
<alex.gaynor@gmail.com>, <boqun.feng@gmail.com>,
<gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
<lossin@kernel.org>, <a.hindborg@kernel.org>,
<aliceryhl@google.com>, <tmgross@umich.edu>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<cjia@nvidia.com>, <smitra@nvidia.com>, <ankita@nvidia.com>,
<aniketa@nvidia.com>, <kwankhede@nvidia.com>,
<targupta@nvidia.com>, <zhiwang@kernel.org>,
<acourbot@nvidia.com>, <joelagnelf@nvidia.com>,
<jhubbard@nvidia.com>, <markus.probst@posteo.de>
Subject: Re: [PATCH v2 1/5] rust/io: factor common I/O helpers into Io trait and specialize Mmio<SIZE>
Date: Fri, 17 Oct 2025 12:56:34 +0200 [thread overview]
Message-ID: <DDKJK7SXG83N.2YZYITMDGTHP@kernel.org> (raw)
In-Reply-To: <20251016210250.15932-2-zhiw@nvidia.com>
On Thu Oct 16, 2025 at 11:02 PM CEST, Zhi Wang wrote:
> diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/regs/macros.rs
> index 8058e1696df9..c2a6547d58cd 100644
> --- a/drivers/gpu/nova-core/regs/macros.rs
> +++ b/drivers/gpu/nova-core/regs/macros.rs
> @@ -609,7 +609,7 @@ impl $name {
> /// Read the register from its address in `io`.
> #[inline(always)]
> pub(crate) fn read<const SIZE: usize, T>(io: &T) -> Self where
> - T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
> + T: ::core::ops::Deref<Target = ::kernel::io::Mmio<SIZE>>,
This should be
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::Io<SIZE>,
instead, otherwise register!() only works for MMIO, but it should work for any
I/O backend.
> +impl<const SIZE: usize> Io<SIZE> for Mmio<SIZE> {
> + /// Returns the base address of this mapping.
> + #[inline]
> + fn addr(&self) -> usize {
> + self.0.addr()
> + }
> +
> + /// Returns the maximum size of this mapping.
> + #[inline]
> + fn maxsize(&self) -> usize {
> + self.0.maxsize()
> + }
> +}
The I/O trait should contain the corresponding read/write accessors, otherwise
we can't easily wire up the register!() macro with arbitrary I/O backends.
I think more specific things, such as relaxed operations can remain MMIO
specific, but all the {try_}{read,write}{8,16,32,64} accessors should be part of
the I/O trait.
next prev parent reply other threads:[~2025-10-17 10:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 21:02 [PATCH v2 0/5] rust: pci: add config space read/write support, take 1 Zhi Wang
2025-10-16 21:02 ` [PATCH v2 1/5] rust/io: factor common I/O helpers into Io trait and specialize Mmio<SIZE> Zhi Wang
2025-10-17 1:26 ` Bjorn Helgaas
2025-10-17 10:56 ` Danilo Krummrich [this message]
2025-10-20 11:44 ` Alexandre Courbot
2025-10-20 19:34 ` John Hubbard
2025-10-20 23:36 ` kernel test robot
2025-10-16 21:02 ` [PATCH v2 2/5] rust: io: factor out MMIO read/write macros Zhi Wang
2025-10-17 11:01 ` Danilo Krummrich
2025-10-16 21:02 ` [PATCH v2 3/5] rust: pci: add a helper to query configuration space size Zhi Wang
2025-10-17 11:09 ` Danilo Krummrich
2025-10-16 21:02 ` [PATCH v2 4/5] rust: pci: add config space read/write support Zhi Wang
2025-10-16 21:02 ` [PATCH v2 5/5] nova-core: test configuration routine Zhi Wang
2025-10-17 4:55 ` Zhi Wang
2025-10-17 11:11 ` Danilo Krummrich
2025-10-21 14:07 ` [PATCH v2 0/5] rust: pci: add config space read/write support, take 1 Alexandre Courbot
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