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Tue, 21 Oct 2025 03:12:14 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 21 Oct 2025 12:10:47 +0200 Message-Id: Subject: Re: [PATCH v2] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries Cc: , , , , , , , "linux-riscv" To: "Hui Min Mina Chou" , , , , , , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251021083105.4029305-1-minachou@andestech.com> In-Reply-To: <20251021083105.4029305-1-minachou@andestech.com> 2025-10-21T16:31:05+08:00, Hui Min Mina Chou : > From: Hui Min Mina Chou > > If multiple VCPUs of the same Guest/VM run on the same Host CPU, > hfence.vvma only flushes that Host CPU=E2=80=99s VS-stage TLB. Other Host= CPUs > may retain stale VS-stage entries. When a VCPU later migrates to a > different Host CPU, it can hit these stale GVA to GPA mappings, causing > unexpected faults in the Guest. > > To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both > G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CP= U. > This ensures that no stale VS-stage mappings remain after VCPU migration. > > Fixes: 92e450507d56 ("RISC-V: KVM: Cleanup stale TLB entries when host CP= U changes") > Signed-off-by: Hui Min Mina Chou > Signed-off-by: Ben Zong-You Xie > --- The vvma flush is not necessary on implementation that have a single TLB for the combined mapping, but there is no good way of detecting that, Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99