[PATCH 0/3] Add NMI Support to RISC-V via SSE

[PATCH 0/3] Add NMI Support to RISC-V via SSE

[Yunhui Cui]

We thank Clément Léger (Rivos Inc.) for his foundational SSE
work ([1]), upon which this patch series builds. This series adds
NMI support to RISC-V via SSE, with two key focuses:
1. A PR to the RISC-V SBI spec ([2]) for unknown NMI handling, with
matching Linux kernel changes.
2. Extending NMI usage to all system scenarios where it boosts
robustness—e.g., stopping CPUs during crashes.

[1] https://lore.kernel.org/all/20250908181717.1997461-1-cleger@rivosinc.com/
[2] https://github.com/riscv-non-isa/riscv-sbi-doc/pull/223

Yunhui Cui (3):
  drivers: firmware: riscv: add SSE NMI support
  riscv: crash: move IPI crash handling logic to crash.c
  riscv: crash: use NMI to stop the CPU

 MAINTAINERS                      |   7 ++
 arch/riscv/include/asm/crash.h   |  17 ++++
 arch/riscv/include/asm/sbi.h     |   2 +
 arch/riscv/include/asm/smp.h     |  14 +++
 arch/riscv/kernel/Makefile       |   2 +-
 arch/riscv/kernel/crash.c        | 111 +++++++++++++++++++++++
 arch/riscv/kernel/smp.c          |  99 +-------------------
 drivers/firmware/riscv/Kconfig   |  10 +++
 drivers/firmware/riscv/Makefile  |   1 +
 drivers/firmware/riscv/sse_nmi.c | 150 +++++++++++++++++++++++++++++++
 include/linux/sse_nmi.h          |   8 ++
 11 files changed, 323 insertions(+), 98 deletions(-)
 create mode 100644 arch/riscv/include/asm/crash.h
 create mode 100644 arch/riscv/kernel/crash.c
 create mode 100644 drivers/firmware/riscv/sse_nmi.c
 create mode 100644 include/linux/sse_nmi.h

-- 
2.39.5

[PATCH 1/3] drivers: firmware: riscv: add SSE NMI support

[Yunhui Cui]

Add support for handling Non-Maskable Interrupts (NMIs) through the
RISC-V Supervisor Software Events (SSE) framework. Since each NMI
type(e.g., unknown NMI, etc.) requires a distinct SSE event, a newfile
sse_nmi.c is introduced to manage their registration and enabling.

Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
---
 MAINTAINERS                      |  7 +++
 arch/riscv/include/asm/sbi.h     |  1 +
 drivers/firmware/riscv/Kconfig   | 10 ++++
 drivers/firmware/riscv/Makefile  |  1 +
 drivers/firmware/riscv/sse_nmi.c | 81 ++++++++++++++++++++++++++++++++
 5 files changed, 100 insertions(+)
 create mode 100644 drivers/firmware/riscv/sse_nmi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 8bf5416953f45..6df6cbec4d85d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22057,6 +22057,13 @@ S:	Maintained
 F:	drivers/firmware/riscv/riscv_sse.c
 F:	include/linux/riscv_sse.h
 
+RISC-V SSE NMI SUPPORT
+M:	Yunhui Cui <cuiyunhui@bytedance.com>
+R:	Xu Lu <luxu.kernel@bytedance.com>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	drivers/firmware/riscv/sse_nmi.c
+
 RISC-V THEAD SoC SUPPORT
 M:	Drew Fustini <fustini@kernel.org>
 M:	Guo Ren <guoren@kernel.org>
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 874cc1d7603a5..52d3fdf2d4cc1 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -486,6 +486,7 @@ enum sbi_sse_attr_id {
 #define SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS	0x00100000
 #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
 #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000
+#define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI		0xffff0001
 #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED	0xffff8000
 
 #define SBI_SSE_EVENT_PLATFORM		BIT(14)
diff --git a/drivers/firmware/riscv/Kconfig b/drivers/firmware/riscv/Kconfig
index ed5b663ac5f91..fd16b4c43cf01 100644
--- a/drivers/firmware/riscv/Kconfig
+++ b/drivers/firmware/riscv/Kconfig
@@ -12,4 +12,14 @@ config RISCV_SBI_SSE
 	  this option provides support to register callbacks on specific SSE
 	  events.
 
+config RISCV_SSE_NMI
+	bool "Enable SBI Supervisor Software Events NMI support"
+	depends on RISCV_SBI_SSE
+	default y
+	help
+	  This option enables support for delivering Non-Maskable Interrupt
+	  (NMI) notifications through the Supervisor Software Events (SSE)
+	  framework. When enabled, the system supports some common NMI features
+	  such as unknown NMI handling.
+
 endmenu
diff --git a/drivers/firmware/riscv/Makefile b/drivers/firmware/riscv/Makefile
index c8795d4bbb2ea..ecf2b31935d9c 100644
--- a/drivers/firmware/riscv/Makefile
+++ b/drivers/firmware/riscv/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-$(CONFIG_RISCV_SBI_SSE)		+= riscv_sbi_sse.o
+obj-$(CONFIG_RISCV_SSE_NMI)		+= sse_nmi.o
diff --git a/drivers/firmware/riscv/sse_nmi.c b/drivers/firmware/riscv/sse_nmi.c
new file mode 100644
index 0000000000000..2c1eaea2bbabc
--- /dev/null
+++ b/drivers/firmware/riscv/sse_nmi.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#define pr_fmt(fmt) "SSE NMI: " fmt
+
+#include <linux/nmi.h>
+#include <linux/riscv_sbi_sse.h>
+#include <linux/sysctl.h>
+
+#include <asm/irq_regs.h>
+#include <asm/sbi.h>
+
+int unknown_nmi_panic;
+static struct sse_event *unknown_nmi_evt;
+static struct ctl_table_header *unknown_nmi_sysctl_header;
+
+static int __init setup_unknown_nmi_panic(char *str)
+{
+	unknown_nmi_panic = 1;
+	return 1;
+}
+__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
+
+const struct ctl_table unknown_nmi_table[] = {
+	{
+		.procname	= "unknown_nmi_panic",
+		.data		= &unknown_nmi_panic,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= proc_dointvec_minmax,
+		.extra1		= SYSCTL_ZERO,
+		.extra2		= SYSCTL_ONE,
+	},
+};
+
+static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
+{
+	pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id());
+
+	if (unknown_nmi_panic)
+		nmi_panic(regs, "NMI: Not continuing");
+
+	pr_emerg("Dazed and confused, but trying to continue\n");
+
+	return 0;
+}
+
+static int unknown_nmi_init(void)
+{
+	int ret;
+
+	unknown_nmi_evt = sse_event_register(SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI, 0,
+					     unknown_nmi_handler, NULL);
+	if (IS_ERR(unknown_nmi_evt))
+		return PTR_ERR(unknown_nmi_evt);
+
+	ret = sse_event_enable(unknown_nmi_evt);
+	if (ret)
+		goto err_unregister;
+
+	unknown_nmi_sysctl_header = register_sysctl("kernel", unknown_nmi_table);
+	if (!unknown_nmi_sysctl_header) {
+		ret = -ENOMEM;
+		goto err_disable;
+	}
+
+	pr_info("Using SSE for unknown NMI event delivery\n");
+	return 0;
+
+err_disable:
+	sse_event_disable(unknown_nmi_evt);
+err_unregister:
+	sse_event_unregister(unknown_nmi_evt);
+	return ret;
+}
+
+static int __init sse_nmi_init(void)
+{
+	return unknown_nmi_init();
+}
+
+late_initcall(sse_nmi_init);
-- 
2.39.5

Re: [PATCH 1/3] drivers: firmware: riscv: add SSE NMI support

[Conor Dooley]

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On Mon, Oct 27, 2025 at 09:34:29PM +0800, Yunhui Cui wrote:
> Add support for handling Non-Maskable Interrupts (NMIs) through the
> RISC-V Supervisor Software Events (SSE) framework. Since each NMI
> type(e.g., unknown NMI, etc.) requires a distinct SSE event, a newfile
> sse_nmi.c is introduced to manage their registration and enabling.
> 
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
>  MAINTAINERS                      |  7 +++
>  arch/riscv/include/asm/sbi.h     |  1 +
>  drivers/firmware/riscv/Kconfig   | 10 ++++
>  drivers/firmware/riscv/Makefile  |  1 +
>  drivers/firmware/riscv/sse_nmi.c | 81 ++++++++++++++++++++++++++++++++
>  5 files changed, 100 insertions(+)
>  create mode 100644 drivers/firmware/riscv/sse_nmi.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8bf5416953f45..6df6cbec4d85d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -22057,6 +22057,13 @@ S:	Maintained
>  F:	drivers/firmware/riscv/riscv_sse.c
>  F:	include/linux/riscv_sse.h
>  
> +RISC-V SSE NMI SUPPORT
> +M:	Yunhui Cui <cuiyunhui@bytedance.com>
> +R:	Xu Lu <luxu.kernel@bytedance.com>
> +L:	linux-riscv@lists.infradead.org
> +S:	Maintained
> +F:	drivers/firmware/riscv/sse_nmi.c

Does actually this need a separate entry?

>  RISC-V THEAD SoC SUPPORT
>  M:	Drew Fustini <fustini@kernel.org>
>  M:	Guo Ren <guoren@kernel.org>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 874cc1d7603a5..52d3fdf2d4cc1 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -486,6 +486,7 @@ enum sbi_sse_attr_id {
>  #define SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS	0x00100000
>  #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
>  #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000

> +#define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI		0xffff0001

Where is this canonically defined?

I looked at the v3 SBI spec and it says:
0xffff0001 - 0xffff3fff Local events reserved for future use
This needs to be marked RFC until this event is in a frozen version of
the SBI spec.

>  #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED	0xffff8000
>  
>  #define SBI_SSE_EVENT_PLATFORM		BIT(14)
> diff --git a/drivers/firmware/riscv/Kconfig b/drivers/firmware/riscv/Kconfig
> index ed5b663ac5f91..fd16b4c43cf01 100644
> --- a/drivers/firmware/riscv/Kconfig
> +++ b/drivers/firmware/riscv/Kconfig
> @@ -12,4 +12,14 @@ config RISCV_SBI_SSE
>  	  this option provides support to register callbacks on specific SSE
>  	  events.
>  
> +config RISCV_SSE_NMI

I think I'd like to see both the filename and Kconfig option match the
established naming for the base sse support.

> +	bool "Enable SBI Supervisor Software Events NMI support"
> +	depends on RISCV_SBI_SSE
> +	default y
> +	help
> +	  This option enables support for delivering Non-Maskable Interrupt
> +	  (NMI) notifications through the Supervisor Software Events (SSE)
> +	  framework.

> When enabled, the system supports some common NMI features
> +	  such as unknown NMI handling.

No, when enabled the _kernel_ supports these things. The code in this
patch seems to fail gracefully when there's no SSE support in the
underlying system, but you should make the option description match
reality.

Cheers,
Conor.

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[PATCH 2/3] riscv: crash: move IPI crash handling logic to crash.c

[Yunhui Cui]

Move IPI crash handling code from smp.c to a new crash.c to
separate concerns and improve code organization, no functional change.

Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
---
 arch/riscv/include/asm/crash.h | 16 ++++++
 arch/riscv/include/asm/smp.h   | 14 +++++
 arch/riscv/kernel/Makefile     |  2 +-
 arch/riscv/kernel/crash.c      | 84 +++++++++++++++++++++++++++++
 arch/riscv/kernel/smp.c        | 99 +---------------------------------
 5 files changed, 117 insertions(+), 98 deletions(-)
 create mode 100644 arch/riscv/include/asm/crash.h
 create mode 100644 arch/riscv/kernel/crash.c

diff --git a/arch/riscv/include/asm/crash.h b/arch/riscv/include/asm/crash.h
new file mode 100644
index 0000000000000..b64df919277d4
--- /dev/null
+++ b/arch/riscv/include/asm/crash.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _ASM_RISC_V_CRASH_H
+#define _ASM_RISC_V_CRASH_H
+
+#ifdef CONFIG_KEXEC_CORE
+void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
+#else
+static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
+{
+	unreachable();
+}
+#endif
+
+#endif
+
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 7ac80e9f22889..ffd7f6f8d25aa 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -12,6 +12,18 @@
 
 #define INVALID_HARTID ULONG_MAX
 
+enum ipi_message_type {
+	IPI_RESCHEDULE,
+	IPI_CALL_FUNC,
+	IPI_CPU_STOP,
+	IPI_CPU_CRASH_STOP,
+	IPI_IRQ_WORK,
+	IPI_TIMER,
+	IPI_CPU_BACKTRACE,
+	IPI_KGDB_ROUNDUP,
+	IPI_MAX
+};
+
 struct seq_file;
 extern unsigned long boot_cpu_hartid;
 
@@ -51,6 +63,8 @@ bool riscv_ipi_have_virq_range(void);
 /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */
 void riscv_ipi_set_virq_range(int virq, int nr);
 
+void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op);
+
 /* Check other CPUs stop or not */
 bool smp_crash_stop_failed(void);
 
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index 16637e01a6b34..f0fd655b113d3 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -107,7 +107,7 @@ endif
 obj-$(CONFIG_HOTPLUG_CPU)	+= cpu-hotplug.o
 obj-$(CONFIG_PARAVIRT)		+= paravirt.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
-obj-$(CONFIG_KEXEC_CORE)	+= kexec_relocate.o crash_save_regs.o machine_kexec.o
+obj-$(CONFIG_KEXEC_CORE)	+= kexec_relocate.o crash_save_regs.o machine_kexec.o crash.o
 obj-$(CONFIG_KEXEC_FILE)	+= kexec_elf.o kexec_image.o machine_kexec_file.o
 obj-$(CONFIG_CRASH_DUMP)	+= crash_dump.o
 obj-$(CONFIG_VMCORE_INFO)	+= vmcore_info.o
diff --git a/arch/riscv/kernel/crash.c b/arch/riscv/kernel/crash.c
new file mode 100644
index 0000000000000..12598bbc2df04
--- /dev/null
+++ b/arch/riscv/kernel/crash.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/cpu.h>
+#include <linux/delay.h>
+#include <linux/kexec.h>
+#include <linux/smp.h>
+#include <linux/sched.h>
+
+#include <asm/cpu_ops.h>
+
+static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
+
+inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
+{
+	crash_save_cpu(regs, cpu);
+
+	atomic_dec(&waiting_for_crash_ipi);
+
+	local_irq_disable();
+
+#ifdef CONFIG_HOTPLUG_CPU
+	if (cpu_has_hotplug(cpu))
+		cpu_ops->cpu_stop();
+#endif
+
+	for (;;)
+		wait_for_interrupt();
+}
+
+/*
+ * The number of CPUs online, not counting this CPU (which may not be
+ * fully online and so not counted in num_online_cpus()).
+ */
+static inline unsigned int num_other_online_cpus(void)
+{
+	unsigned int this_cpu_online = cpu_online(smp_processor_id());
+
+	return num_online_cpus() - this_cpu_online;
+}
+
+void crash_smp_send_stop(void)
+{
+	static int cpus_stopped;
+	cpumask_t mask;
+	unsigned long timeout;
+
+	/*
+	 * This function can be called twice in panic path, but obviously
+	 * we execute this only once.
+	 */
+	if (cpus_stopped)
+		return;
+
+	cpus_stopped = 1;
+
+	/*
+	 * If this cpu is the only one alive at this point in time, online or
+	 * not, there are no stop messages to be sent around, so just back out.
+	 */
+	if (num_other_online_cpus() == 0)
+		return;
+
+	cpumask_copy(&mask, cpu_online_mask);
+	cpumask_clear_cpu(smp_processor_id(), &mask);
+
+	atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
+
+	pr_crit("SMP: stopping secondary CPUs\n");
+	send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
+
+	/* Wait up to one second for other CPUs to stop */
+	timeout = USEC_PER_SEC;
+	while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--)
+		udelay(1);
+
+	if (atomic_read(&waiting_for_crash_ipi) > 0)
+		pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
+			cpumask_pr_args(&mask));
+}
+
+bool smp_crash_stop_failed(void)
+{
+	return (atomic_read(&waiting_for_crash_ipi) > 0);
+}
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index e650dec448176..c4191b15b3547 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -24,22 +24,11 @@
 #include <linux/irq_work.h>
 #include <linux/nmi.h>
 
+#include <asm/crash.h>
 #include <asm/tlbflush.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu_ops.h>
 
-enum ipi_message_type {
-	IPI_RESCHEDULE,
-	IPI_CALL_FUNC,
-	IPI_CPU_STOP,
-	IPI_CPU_CRASH_STOP,
-	IPI_IRQ_WORK,
-	IPI_TIMER,
-	IPI_CPU_BACKTRACE,
-	IPI_KGDB_ROUNDUP,
-	IPI_MAX
-};
-
 unsigned long __cpuid_to_hartid_map[NR_CPUS] __ro_after_init = {
 	[0 ... NR_CPUS-1] = INVALID_HARTID
 };
@@ -75,33 +64,7 @@ static void ipi_stop(void)
 		wait_for_interrupt();
 }
 
-#ifdef CONFIG_KEXEC_CORE
-static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
-
-static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
-{
-	crash_save_cpu(regs, cpu);
-
-	atomic_dec(&waiting_for_crash_ipi);
-
-	local_irq_disable();
-
-#ifdef CONFIG_HOTPLUG_CPU
-	if (cpu_has_hotplug(cpu))
-		cpu_ops->cpu_stop();
-#endif
-
-	for(;;)
-		wait_for_interrupt();
-}
-#else
-static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
-{
-	unreachable();
-}
-#endif
-
-static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
+void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
 {
 	__ipi_send_mask(ipi_desc[op], mask);
 }
@@ -276,64 +239,6 @@ void smp_send_stop(void)
 			   cpumask_pr_args(cpu_online_mask));
 }
 
-#ifdef CONFIG_KEXEC_CORE
-/*
- * The number of CPUs online, not counting this CPU (which may not be
- * fully online and so not counted in num_online_cpus()).
- */
-static inline unsigned int num_other_online_cpus(void)
-{
-	unsigned int this_cpu_online = cpu_online(smp_processor_id());
-
-	return num_online_cpus() - this_cpu_online;
-}
-
-void crash_smp_send_stop(void)
-{
-	static int cpus_stopped;
-	cpumask_t mask;
-	unsigned long timeout;
-
-	/*
-	 * This function can be called twice in panic path, but obviously
-	 * we execute this only once.
-	 */
-	if (cpus_stopped)
-		return;
-
-	cpus_stopped = 1;
-
-	/*
-	 * If this cpu is the only one alive at this point in time, online or
-	 * not, there are no stop messages to be sent around, so just back out.
-	 */
-	if (num_other_online_cpus() == 0)
-		return;
-
-	cpumask_copy(&mask, cpu_online_mask);
-	cpumask_clear_cpu(smp_processor_id(), &mask);
-
-	atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
-
-	pr_crit("SMP: stopping secondary CPUs\n");
-	send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
-
-	/* Wait up to one second for other CPUs to stop */
-	timeout = USEC_PER_SEC;
-	while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--)
-		udelay(1);
-
-	if (atomic_read(&waiting_for_crash_ipi) > 0)
-		pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
-			cpumask_pr_args(&mask));
-}
-
-bool smp_crash_stop_failed(void)
-{
-	return (atomic_read(&waiting_for_crash_ipi) > 0);
-}
-#endif
-
 void arch_smp_send_reschedule(int cpu)
 {
 	send_ipi_single(cpu, IPI_RESCHEDULE);
-- 
2.39.5

[PATCH 3/3] riscv: crash: use NMI to stop the CPU

[Yunhui Cui]

NMI is more robust than IPI for stopping CPUs during crashes,
especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
eventid to implement NMI for stopping CPUs.

Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
---
 arch/riscv/include/asm/crash.h   |  1 +
 arch/riscv/include/asm/sbi.h     |  1 +
 arch/riscv/kernel/crash.c        | 31 +++++++++++++-
 drivers/firmware/riscv/sse_nmi.c | 71 +++++++++++++++++++++++++++++++-
 include/linux/sse_nmi.h          |  8 ++++
 5 files changed, 109 insertions(+), 3 deletions(-)
 create mode 100644 include/linux/sse_nmi.h

diff --git a/arch/riscv/include/asm/crash.h b/arch/riscv/include/asm/crash.h
index b64df919277d4..5076f297cbc15 100644
--- a/arch/riscv/include/asm/crash.h
+++ b/arch/riscv/include/asm/crash.h
@@ -5,6 +5,7 @@
 
 #ifdef CONFIG_KEXEC_CORE
 void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
+void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
 #else
 static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
 {
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 52d3fdf2d4cc1..65cce85237879 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
 #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
 #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000
 #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI		0xffff0001
+#define SBI_SSE_EVENT_LOCAL_CRASH_NMI		0xffff0002
 #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED	0xffff8000
 
 #define SBI_SSE_EVENT_PLATFORM		BIT(14)
diff --git a/arch/riscv/kernel/crash.c b/arch/riscv/kernel/crash.c
index 12598bbc2df04..9f3f0becfdd95 100644
--- a/arch/riscv/kernel/crash.c
+++ b/arch/riscv/kernel/crash.c
@@ -3,14 +3,16 @@
 #include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/kexec.h>
+#include <linux/sse_nmi.h>
 #include <linux/smp.h>
 #include <linux/sched.h>
 
+#include <asm/crash.h>
 #include <asm/cpu_ops.h>
 
 static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
 
-inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
+void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
 {
 	crash_save_cpu(regs, cpu);
 
@@ -27,6 +29,11 @@ inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
 		wait_for_interrupt();
 }
 
+inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
+{
+	cpu_crash_stop(cpu, regs);
+}
+
 /*
  * The number of CPUs online, not counting this CPU (which may not be
  * fully online and so not counted in num_online_cpus()).
@@ -38,6 +45,24 @@ static inline unsigned int num_other_online_cpus(void)
 	return num_online_cpus() - this_cpu_online;
 }
 
+#ifdef CONFIG_RISCV_SSE_NMI
+static int send_nmi_stop_cpu(cpumask_t *mask)
+{
+	unsigned int cpu;
+	int ret = 0;
+
+	for_each_cpu(cpu, mask)
+		ret += carsh_nmi_stop_cpu(cpu);
+
+	return ret;
+}
+#else
+static inline int send_nmi_stop_cpu(cpumask_t *mask)
+{
+	return -EOPNOTSUPP;
+}
+#endif
+
 void crash_smp_send_stop(void)
 {
 	static int cpus_stopped;
@@ -66,7 +91,9 @@ void crash_smp_send_stop(void)
 	atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
 
 	pr_crit("SMP: stopping secondary CPUs\n");
-	send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
+
+	if (send_nmi_stop_cpu(&mask))
+		send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
 
 	/* Wait up to one second for other CPUs to stop */
 	timeout = USEC_PER_SEC;
diff --git a/drivers/firmware/riscv/sse_nmi.c b/drivers/firmware/riscv/sse_nmi.c
index 2c1eaea2bbabc..152d787075345 100644
--- a/drivers/firmware/riscv/sse_nmi.c
+++ b/drivers/firmware/riscv/sse_nmi.c
@@ -4,13 +4,16 @@
 
 #include <linux/nmi.h>
 #include <linux/riscv_sbi_sse.h>
+#include <linux/sse_nmi.h>
 #include <linux/sysctl.h>
 
+#include <asm/crash.h>
 #include <asm/irq_regs.h>
 #include <asm/sbi.h>
 
 int unknown_nmi_panic;
 static struct sse_event *unknown_nmi_evt;
+static struct sse_event *crash_nmi_evt;
 static struct ctl_table_header *unknown_nmi_sysctl_header;
 
 static int __init setup_unknown_nmi_panic(char *str)
@@ -32,6 +35,12 @@ const struct ctl_table unknown_nmi_table[] = {
 	},
 };
 
+static inline struct sbiret sbi_sse_ecall(int fid, unsigned long arg0,
+					  unsigned long arg1)
+{
+	return sbi_ecall(SBI_EXT_SSE, fid, arg0, arg1, 0, 0, 0, 0);
+}
+
 static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
 {
 	pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id());
@@ -73,9 +82,69 @@ static int unknown_nmi_init(void)
 	return ret;
 }
 
+#ifdef CONFIG_KEXEC_CORE
+int carsh_nmi_stop_cpu(unsigned int cpu)
+{
+	unsigned int hart_id = cpuid_to_hartid_map(cpu);
+	u32 evt = SBI_SSE_EVENT_LOCAL_CRASH_NMI;
+	struct sbiret ret;
+
+	ret = sbi_sse_ecall(SBI_SSE_EVENT_INJECT, evt, hart_id);
+	if (ret.error) {
+		pr_err("Failed to signal event %x, error %ld\n", evt, ret.error);
+		return sbi_err_map_linux_errno(ret.error);
+	}
+
+	return 0;
+}
+
+static int crash_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
+{
+	cpu_crash_stop(smp_processor_id(), regs);
+
+	return 0;
+}
+
+static int crash_nmi_init(void)
+{
+	int ret;
+
+	crash_nmi_evt = sse_event_register(SBI_SSE_EVENT_LOCAL_CRASH_NMI, 0,
+				 crash_nmi_handler, NULL);
+	if (IS_ERR(crash_nmi_evt))
+		return PTR_ERR(crash_nmi_evt);
+
+	ret = sse_event_enable(crash_nmi_evt);
+	if (ret) {
+		sse_event_unregister(crash_nmi_evt);
+		return ret;
+	}
+
+	pr_info("Using SSE for crash NMI event delivery\n");
+
+	return 0;
+}
+#endif
+
 static int __init sse_nmi_init(void)
 {
-	return unknown_nmi_init();
+	int ret;
+
+	ret = unknown_nmi_init();
+	if (ret) {
+		pr_err("Unknown_nmi_init failed with error %d\n", ret);
+		return ret;
+	}
+
+#ifdef CONFIG_KEXEC_CORE
+	ret = crash_nmi_init();
+	if (ret) {
+		pr_err("Crash_nmi_init failed with error %d\n", ret);
+		return ret;
+	}
+#endif
+
+	return 0;
 }
 
 late_initcall(sse_nmi_init);
diff --git a/include/linux/sse_nmi.h b/include/linux/sse_nmi.h
new file mode 100644
index 0000000000000..548a348ac0a46
--- /dev/null
+++ b/include/linux/sse_nmi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __LINUX_RISCV_SSE_NMI_H
+#define __LINUX_RISCV_SSE_NMI_H
+
+int carsh_nmi_stop_cpu(unsigned int cpu);
+
+#endif
-- 
2.39.5

Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU

[Conor Dooley]

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On Mon, Oct 27, 2025 at 09:34:31PM +0800, Yunhui Cui wrote:
> NMI is more robust than IPI for stopping CPUs during crashes,
> especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
> eventid to implement NMI for stopping CPUs.
> 
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
>  arch/riscv/include/asm/crash.h   |  1 +
>  arch/riscv/include/asm/sbi.h     |  1 +
>  arch/riscv/kernel/crash.c        | 31 +++++++++++++-
>  drivers/firmware/riscv/sse_nmi.c | 71 +++++++++++++++++++++++++++++++-
>  include/linux/sse_nmi.h          |  8 ++++
>  5 files changed, 109 insertions(+), 3 deletions(-)
>  create mode 100644 include/linux/sse_nmi.h
> 
> diff --git a/arch/riscv/include/asm/crash.h b/arch/riscv/include/asm/crash.h
> index b64df919277d4..5076f297cbc15 100644
> --- a/arch/riscv/include/asm/crash.h
> +++ b/arch/riscv/include/asm/crash.h
> @@ -5,6 +5,7 @@
>  
>  #ifdef CONFIG_KEXEC_CORE
>  void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
> +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
>  #else
>  static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
>  {
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 52d3fdf2d4cc1..65cce85237879 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
>  #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
>  #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000
>  #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI		0xffff0001
> +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI		0xffff0002
>  #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED	0xffff8000
>  
>  #define SBI_SSE_EVENT_PLATFORM		BIT(14)
> diff --git a/arch/riscv/kernel/crash.c b/arch/riscv/kernel/crash.c
> index 12598bbc2df04..9f3f0becfdd95 100644
> --- a/arch/riscv/kernel/crash.c
> +++ b/arch/riscv/kernel/crash.c
> @@ -3,14 +3,16 @@
>  #include <linux/cpu.h>
>  #include <linux/delay.h>
>  #include <linux/kexec.h>
> +#include <linux/sse_nmi.h>
>  #include <linux/smp.h>
>  #include <linux/sched.h>
>  
> +#include <asm/crash.h>
>  #include <asm/cpu_ops.h>
>  
>  static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
>  
> -inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
>  {
>  	crash_save_cpu(regs, cpu);
>  
> @@ -27,6 +29,11 @@ inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
>  		wait_for_interrupt();
>  }
>  
> +inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> +{
> +	cpu_crash_stop(cpu, regs);
> +}
> +
>  /*
>   * The number of CPUs online, not counting this CPU (which may not be
>   * fully online and so not counted in num_online_cpus()).
> @@ -38,6 +45,24 @@ static inline unsigned int num_other_online_cpus(void)
>  	return num_online_cpus() - this_cpu_online;
>  }
>  
> +#ifdef CONFIG_RISCV_SSE_NMI
> +static int send_nmi_stop_cpu(cpumask_t *mask)
> +{
> +	unsigned int cpu;
> +	int ret = 0;
> +
> +	for_each_cpu(cpu, mask)
> +		ret += carsh_nmi_stop_cpu(cpu);

+= ? I don't really get why this sort of overcomplication is needed, why
not just return immediately here with a real error code, since you're
going to have to go to the ipi fallback anyway?

> +
> +	return ret;
> +}
> +#else
> +static inline int send_nmi_stop_cpu(cpumask_t *mask)
> +{
> +	return -EOPNOTSUPP;
> +}
> +#endif
> +
>  void crash_smp_send_stop(void)
>  {
>  	static int cpus_stopped;
> @@ -66,7 +91,9 @@ void crash_smp_send_stop(void)
>  	atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
>  
>  	pr_crit("SMP: stopping secondary CPUs\n");
> -	send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
> +
> +	if (send_nmi_stop_cpu(&mask))
> +		send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
>  
>  	/* Wait up to one second for other CPUs to stop */
>  	timeout = USEC_PER_SEC;
> diff --git a/drivers/firmware/riscv/sse_nmi.c b/drivers/firmware/riscv/sse_nmi.c
> index 2c1eaea2bbabc..152d787075345 100644
> --- a/drivers/firmware/riscv/sse_nmi.c
> +++ b/drivers/firmware/riscv/sse_nmi.c
> @@ -4,13 +4,16 @@
>  
>  #include <linux/nmi.h>
>  #include <linux/riscv_sbi_sse.h>
> +#include <linux/sse_nmi.h>
>  #include <linux/sysctl.h>
>  
> +#include <asm/crash.h>
>  #include <asm/irq_regs.h>
>  #include <asm/sbi.h>
>  
>  int unknown_nmi_panic;
>  static struct sse_event *unknown_nmi_evt;
> +static struct sse_event *crash_nmi_evt;
>  static struct ctl_table_header *unknown_nmi_sysctl_header;
>  
>  static int __init setup_unknown_nmi_panic(char *str)
> @@ -32,6 +35,12 @@ const struct ctl_table unknown_nmi_table[] = {
>  	},
>  };
>  
> +static inline struct sbiret sbi_sse_ecall(int fid, unsigned long arg0,
> +					  unsigned long arg1)
> +{
> +	return sbi_ecall(SBI_EXT_SSE, fid, arg0, arg1, 0, 0, 0, 0);
> +}
> +
>  static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
>  {
>  	pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id());
> @@ -73,9 +82,69 @@ static int unknown_nmi_init(void)
>  	return ret;
>  }
>  
> +#ifdef CONFIG_KEXEC_CORE
> +int carsh_nmi_stop_cpu(unsigned int cpu)

typo: crash

> +{
> +	unsigned int hart_id = cpuid_to_hartid_map(cpu);
> +	u32 evt = SBI_SSE_EVENT_LOCAL_CRASH_NMI;
> +	struct sbiret ret;
> +
> +	ret = sbi_sse_ecall(SBI_SSE_EVENT_INJECT, evt, hart_id);
> +	if (ret.error) {
> +		pr_err("Failed to signal event %x, error %ld\n", evt, ret.error);

Isn't this going to emit pointless (and maybe confusing) error messages
on systems that enable the option but don't support SSE? And it's going
to be one for each secondary CPU too.

> +		return sbi_err_map_linux_errno(ret.error);
> +	}
> +
> +	return 0;
> +}
> +
> +static int crash_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
> +{
> +	cpu_crash_stop(smp_processor_id(), regs);
> +
> +	return 0;
> +}
> +
> +static int crash_nmi_init(void)
> +{
> +	int ret;
> +
> +	crash_nmi_evt = sse_event_register(SBI_SSE_EVENT_LOCAL_CRASH_NMI, 0,
> +				 crash_nmi_handler, NULL);
> +	if (IS_ERR(crash_nmi_evt))
> +		return PTR_ERR(crash_nmi_evt);
> +
> +	ret = sse_event_enable(crash_nmi_evt);
> +	if (ret) {
> +		sse_event_unregister(crash_nmi_evt);
> +		return ret;
> +	}
> +
> +	pr_info("Using SSE for crash NMI event delivery\n");
> +
> +	return 0;
> +}
> +#endif
> +
>  static int __init sse_nmi_init(void)
>  {
> -	return unknown_nmi_init();
> +	int ret;
> +
> +	ret = unknown_nmi_init();
> +	if (ret) {
> +		pr_err("Unknown_nmi_init failed with error %d\n", ret);
> +		return ret;
> +	}

This change looks like it shouldn't be in this patch, if you want it to
print an error, just do that from the start?

> +
> +#ifdef CONFIG_KEXEC_CORE

Can this be IS_ENABLED() or does crash_nmi_init() not have a stub?

> +	ret = crash_nmi_init();
> +	if (ret) {
> +		pr_err("Crash_nmi_init failed with error %d\n", ret);
> +		return ret;
> +	}
> +#endif
> +
> +	return 0;
>  }
>  
>  late_initcall(sse_nmi_init);
> diff --git a/include/linux/sse_nmi.h b/include/linux/sse_nmi.h
> new file mode 100644
> index 0000000000000..548a348ac0a46
> --- /dev/null
> +++ b/include/linux/sse_nmi.h
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __LINUX_RISCV_SSE_NMI_H
> +#define __LINUX_RISCV_SSE_NMI_H
> +
> +int carsh_nmi_stop_cpu(unsigned int cpu);
> +
> +#endif
> -- 
> 2.39.5
> 

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Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU

[Radim Krčmář]

2025-10-28T10:42:12+00:00, Conor Dooley <conor@kernel.org>:
> On Mon, Oct 27, 2025 at 09:34:31PM +0800, Yunhui Cui wrote:
>> NMI is more robust than IPI for stopping CPUs during crashes,
>> especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
>> eventid to implement NMI for stopping CPUs.
>> 
>> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>> ---
>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>> @@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
>>  #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
>>  #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000
>>  #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI		0xffff0001
>> +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI		0xffff0002

This event isn't defined in the SBI pull request.

I assume it's a pure software event that the platform shouldn't inject.
If we want to reserve more events for software use, why not make them
generic, like SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED?

Thanks.

Re: [External] Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU

[yunhui cui]

Hi Radim,

On Tue, Oct 28, 2025 at 8:36 PM Radim Krčmář <rkrcmar@ventanamicro.com> wrote:
>
> 2025-10-28T10:42:12+00:00, Conor Dooley <conor@kernel.org>:
> > On Mon, Oct 27, 2025 at 09:34:31PM +0800, Yunhui Cui wrote:
> >> NMI is more robust than IPI for stopping CPUs during crashes,
> >> especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
> >> eventid to implement NMI for stopping CPUs.
> >>
> >> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> >> ---
> >> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> >> @@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
> >>  #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS   0x00108000
> >>  #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED       0xffff0000
> >>  #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI             0xffff0001
> >> +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI               0xffff0002
>
> This event isn't defined in the SBI pull request.
>
> I assume it's a pure software event that the platform shouldn't inject.
> If we want to reserve more events for software use, why not make them
> generic, like SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED?

In fact, it's not just crash NMI, but also stop NMI, kgdb NMI, etc. An
event can only register one SSE handler. If all use
SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED, we'll have to execute each
different NMI handler in sequence within the SSE handler, with each
NMI handler checking for itself if there are NMIs of its type to
process.
Is that what you mean too?

>
> Thanks.

Thanks,
Yunhui

Re: [External] Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU

[Radim Krčmář]

2025-11-03T22:10:25+08:00, yunhui cui <cuiyunhui@bytedance.com>:
> Hi Radim,
>
> On Tue, Oct 28, 2025 at 8:36 PM Radim Krčmář <rkrcmar@ventanamicro.com> wrote:
>>
>> 2025-10-28T10:42:12+00:00, Conor Dooley <conor@kernel.org>:
>> > On Mon, Oct 27, 2025 at 09:34:31PM +0800, Yunhui Cui wrote:
>> >> NMI is more robust than IPI for stopping CPUs during crashes,
>> >> especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
>> >> eventid to implement NMI for stopping CPUs.
>> >>
>> >> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>> >> ---
>> >> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>> >> @@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
>> >>  #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS   0x00108000
>> >>  #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED       0xffff0000
>> >>  #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI             0xffff0001
>> >> +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI               0xffff0002
>>
>> This event isn't defined in the SBI pull request.
>>
>> I assume it's a pure software event that the platform shouldn't inject.
>> If we want to reserve more events for software use, why not make them
>> generic, like SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED?
>
> In fact, it's not just crash NMI, but also stop NMI, kgdb NMI, etc. An
> event can only register one SSE handler. If all use
> SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED, we'll have to execute each
> different NMI handler in sequence within the SSE handler, with each
> NMI handler checking for itself if there are NMIs of its type to
> process.
> Is that what you mean too?

My main point is that a platform doesn't seem to care what 0xffff0002 is
used for, so SBI could just assign a range of SSE event vectors for
software use, without trying to be overly specific about the purpose.
(I don't see a meaningful difference between 0xffff0000 and 0xffff0002.)

Demultiplexing a single SSE event vector is possible if event handlers
don't have to (or shouldn't) preempt each other.
I assume that we do need at least two software SSE event vectors, since
we should be able to interrupt other SSE handlers to execute the SSE
crash handler.
Do you think that two software SSE events are sufficient, or should we
aim to reserve more in SBI?

Thanks.

Re: [External] Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU

[yunhui cui]

Hi Conor,

On Tue, Oct 28, 2025 at 6:42 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Mon, Oct 27, 2025 at 09:34:31PM +0800, Yunhui Cui wrote:
> > NMI is more robust than IPI for stopping CPUs during crashes,
> > especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
> > eventid to implement NMI for stopping CPUs.
> >
> > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > ---
> >  arch/riscv/include/asm/crash.h   |  1 +
> >  arch/riscv/include/asm/sbi.h     |  1 +
> >  arch/riscv/kernel/crash.c        | 31 +++++++++++++-
> >  drivers/firmware/riscv/sse_nmi.c | 71 +++++++++++++++++++++++++++++++-
> >  include/linux/sse_nmi.h          |  8 ++++
> >  5 files changed, 109 insertions(+), 3 deletions(-)
> >  create mode 100644 include/linux/sse_nmi.h
> >
> > diff --git a/arch/riscv/include/asm/crash.h b/arch/riscv/include/asm/crash.h
> > index b64df919277d4..5076f297cbc15 100644
> > --- a/arch/riscv/include/asm/crash.h
> > +++ b/arch/riscv/include/asm/crash.h
> > @@ -5,6 +5,7 @@
> >
> >  #ifdef CONFIG_KEXEC_CORE
> >  void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
> > +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
> >  #else
> >  static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> >  {
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index 52d3fdf2d4cc1..65cce85237879 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
> >  #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS    0x00108000
> >  #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED        0xffff0000
> >  #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI              0xffff0001
> > +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI                0xffff0002
> >  #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED       0xffff8000
> >
> >  #define SBI_SSE_EVENT_PLATFORM               BIT(14)
> > diff --git a/arch/riscv/kernel/crash.c b/arch/riscv/kernel/crash.c
> > index 12598bbc2df04..9f3f0becfdd95 100644
> > --- a/arch/riscv/kernel/crash.c
> > +++ b/arch/riscv/kernel/crash.c
> > @@ -3,14 +3,16 @@
> >  #include <linux/cpu.h>
> >  #include <linux/delay.h>
> >  #include <linux/kexec.h>
> > +#include <linux/sse_nmi.h>
> >  #include <linux/smp.h>
> >  #include <linux/sched.h>
> >
> > +#include <asm/crash.h>
> >  #include <asm/cpu_ops.h>
> >
> >  static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
> >
> > -inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> > +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> >  {
> >       crash_save_cpu(regs, cpu);
> >
> > @@ -27,6 +29,11 @@ inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> >               wait_for_interrupt();
> >  }
> >
> > +inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> > +{
> > +     cpu_crash_stop(cpu, regs);
> > +}
> > +
> >  /*
> >   * The number of CPUs online, not counting this CPU (which may not be
> >   * fully online and so not counted in num_online_cpus()).
> > @@ -38,6 +45,24 @@ static inline unsigned int num_other_online_cpus(void)
> >       return num_online_cpus() - this_cpu_online;
> >  }
> >
> > +#ifdef CONFIG_RISCV_SSE_NMI
> > +static int send_nmi_stop_cpu(cpumask_t *mask)
> > +{
> > +     unsigned int cpu;
> > +     int ret = 0;
> > +
> > +     for_each_cpu(cpu, mask)
> > +             ret += carsh_nmi_stop_cpu(cpu);
>
> += ? I don't really get why this sort of overcomplication is needed, why
> not just return immediately here with a real error code, since you're
> going to have to go to the ipi fallback anyway?

A cpumask may be needed to mark the CPUs where NMI failed, and then
continue to stop the CPUs via IPI.

>
> > +
> > +     return ret;
> > +}
> > +#else
> > +static inline int send_nmi_stop_cpu(cpumask_t *mask)
> > +{
> > +     return -EOPNOTSUPP;
> > +}
> > +#endif
> > +
> >  void crash_smp_send_stop(void)
> >  {
> >       static int cpus_stopped;
> > @@ -66,7 +91,9 @@ void crash_smp_send_stop(void)
> >       atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
> >
> >       pr_crit("SMP: stopping secondary CPUs\n");
> > -     send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
> > +
> > +     if (send_nmi_stop_cpu(&mask))
> > +             send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
> >
> >       /* Wait up to one second for other CPUs to stop */
> >       timeout = USEC_PER_SEC;
> > diff --git a/drivers/firmware/riscv/sse_nmi.c b/drivers/firmware/riscv/sse_nmi.c
> > index 2c1eaea2bbabc..152d787075345 100644
> > --- a/drivers/firmware/riscv/sse_nmi.c
> > +++ b/drivers/firmware/riscv/sse_nmi.c
> > @@ -4,13 +4,16 @@
> >
> >  #include <linux/nmi.h>
> >  #include <linux/riscv_sbi_sse.h>
> > +#include <linux/sse_nmi.h>
> >  #include <linux/sysctl.h>
> >
> > +#include <asm/crash.h>
> >  #include <asm/irq_regs.h>
> >  #include <asm/sbi.h>
> >
> >  int unknown_nmi_panic;
> >  static struct sse_event *unknown_nmi_evt;
> > +static struct sse_event *crash_nmi_evt;
> >  static struct ctl_table_header *unknown_nmi_sysctl_header;
> >
> >  static int __init setup_unknown_nmi_panic(char *str)
> > @@ -32,6 +35,12 @@ const struct ctl_table unknown_nmi_table[] = {
> >       },
> >  };
> >
> > +static inline struct sbiret sbi_sse_ecall(int fid, unsigned long arg0,
> > +                                       unsigned long arg1)
> > +{
> > +     return sbi_ecall(SBI_EXT_SSE, fid, arg0, arg1, 0, 0, 0, 0);
> > +}
> > +
> >  static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
> >  {
> >       pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id());
> > @@ -73,9 +82,69 @@ static int unknown_nmi_init(void)
> >       return ret;
> >  }
> >
> > +#ifdef CONFIG_KEXEC_CORE
> > +int carsh_nmi_stop_cpu(unsigned int cpu)
>
> typo: crash

Okay.

>
> > +{
> > +     unsigned int hart_id = cpuid_to_hartid_map(cpu);
> > +     u32 evt = SBI_SSE_EVENT_LOCAL_CRASH_NMI;
> > +     struct sbiret ret;
> > +
> > +     ret = sbi_sse_ecall(SBI_SSE_EVENT_INJECT, evt, hart_id);
> > +     if (ret.error) {
> > +             pr_err("Failed to signal event %x, error %ld\n", evt, ret.error);
>
> Isn't this going to emit pointless (and maybe confusing) error messages
> on systems that enable the option but don't support SSE? And it's going
> to be one for each secondary CPU too.

Okay, I'll fix this in the next version.

>
> > +             return sbi_err_map_linux_errno(ret.error);
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static int crash_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
> > +{
> > +     cpu_crash_stop(smp_processor_id(), regs);
> > +
> > +     return 0;
> > +}
> > +
> > +static int crash_nmi_init(void)
> > +{
> > +     int ret;
> > +
> > +     crash_nmi_evt = sse_event_register(SBI_SSE_EVENT_LOCAL_CRASH_NMI, 0,
> > +                              crash_nmi_handler, NULL);
> > +     if (IS_ERR(crash_nmi_evt))
> > +             return PTR_ERR(crash_nmi_evt);
> > +
> > +     ret = sse_event_enable(crash_nmi_evt);
> > +     if (ret) {
> > +             sse_event_unregister(crash_nmi_evt);
> > +             return ret;
> > +     }
> > +
> > +     pr_info("Using SSE for crash NMI event delivery\n");
> > +
> > +     return 0;
> > +}
> > +#endif
> > +
> >  static int __init sse_nmi_init(void)
> >  {
> > -     return unknown_nmi_init();
> > +     int ret;
> > +
> > +     ret = unknown_nmi_init();
> > +     if (ret) {
> > +             pr_err("Unknown_nmi_init failed with error %d\n", ret);
> > +             return ret;
> > +     }
>
> This change looks like it shouldn't be in this patch, if you want it to
> print an error, just do that from the start?

Okay.

>
> > +
> > +#ifdef CONFIG_KEXEC_CORE
>
> Can this be IS_ENABLED() or does crash_nmi_init() not have a stub?

I'll add a stub function in the next version, so no more #ifdef
CONFIG_KEXEC_CORE here.

>
> > +     ret = crash_nmi_init();
> > +     if (ret) {
> > +             pr_err("Crash_nmi_init failed with error %d\n", ret);
> > +             return ret;
> > +     }
> > +#endif
> > +
> > +     return 0;
> >  }
> >
> >  late_initcall(sse_nmi_init);
> > diff --git a/include/linux/sse_nmi.h b/include/linux/sse_nmi.h
> > new file mode 100644
> > index 0000000000000..548a348ac0a46
> > --- /dev/null
> > +++ b/include/linux/sse_nmi.h
> > @@ -0,0 +1,8 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +
> > +#ifndef __LINUX_RISCV_SSE_NMI_H
> > +#define __LINUX_RISCV_SSE_NMI_H
> > +
> > +int carsh_nmi_stop_cpu(unsigned int cpu);
> > +
> > +#endif
> > --
> > 2.39.5
> >

Thanks,
Yunhui

Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU

[Atish Patra]

On 10/27/25 6:34 AM, Yunhui Cui wrote:
> NMI is more robust than IPI for stopping CPUs during crashes,
> especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
> eventid to implement NMI for stopping CPUs.
> 

Resending it again as my previous response was rejected due to 
gmail/html issue.

This should be used as the last resort instead of the preferred approach 
for below reasons.

1. Invoking SSE on this path may lead to some race conditions if 
interruption is enabled.
2. With AIA IPI will be faster than SSE if interrupt is enabled.

Can we do a hybrid approach where we use CRASH_NMI (or SOFTWARE_INJECTED 
event) only when IPI fails.
Looking at other architecture implementations, it already does something 
similar.

> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
>   arch/riscv/include/asm/crash.h   |  1 +
>   arch/riscv/include/asm/sbi.h     |  1 +
>   arch/riscv/kernel/crash.c        | 31 +++++++++++++-
>   drivers/firmware/riscv/sse_nmi.c | 71 +++++++++++++++++++++++++++++++-
>   include/linux/sse_nmi.h          |  8 ++++
>   5 files changed, 109 insertions(+), 3 deletions(-)
>   create mode 100644 include/linux/sse_nmi.h
> 
> diff --git a/arch/riscv/include/asm/crash.h b/arch/riscv/include/asm/crash.h
> index b64df919277d4..5076f297cbc15 100644
> --- a/arch/riscv/include/asm/crash.h
> +++ b/arch/riscv/include/asm/crash.h
> @@ -5,6 +5,7 @@
>   
>   #ifdef CONFIG_KEXEC_CORE
>   void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
> +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs);
>   #else
>   static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
>   {
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 52d3fdf2d4cc1..65cce85237879 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
>   #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
>   #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000
>   #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI		0xffff0001
> +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI		0xffff0002
>   #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED	0xffff8000
>   
>   #define SBI_SSE_EVENT_PLATFORM		BIT(14)
> diff --git a/arch/riscv/kernel/crash.c b/arch/riscv/kernel/crash.c
> index 12598bbc2df04..9f3f0becfdd95 100644
> --- a/arch/riscv/kernel/crash.c
> +++ b/arch/riscv/kernel/crash.c
> @@ -3,14 +3,16 @@
>   #include <linux/cpu.h>
>   #include <linux/delay.h>
>   #include <linux/kexec.h>
> +#include <linux/sse_nmi.h>
>   #include <linux/smp.h>
>   #include <linux/sched.h>
>   
> +#include <asm/crash.h>
>   #include <asm/cpu_ops.h>
>   
>   static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
>   
> -inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
>   {
>   	crash_save_cpu(regs, cpu);
>   
> @@ -27,6 +29,11 @@ inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
>   		wait_for_interrupt();
>   }
>   
> +inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
> +{
> +	cpu_crash_stop(cpu, regs);
> +}
> +
>   /*
>    * The number of CPUs online, not counting this CPU (which may not be
>    * fully online and so not counted in num_online_cpus()).
> @@ -38,6 +45,24 @@ static inline unsigned int num_other_online_cpus(void)
>   	return num_online_cpus() - this_cpu_online;
>   }
>   
> +#ifdef CONFIG_RISCV_SSE_NMI
> +static int send_nmi_stop_cpu(cpumask_t *mask)
> +{
> +	unsigned int cpu;
> +	int ret = 0;
> +
> +	for_each_cpu(cpu, mask)
> +		ret += carsh_nmi_stop_cpu(cpu);
> +
> +	return ret;
> +}
> +#else
> +static inline int send_nmi_stop_cpu(cpumask_t *mask)
> +{
> +	return -EOPNOTSUPP;
> +}
> +#endif
> +
>   void crash_smp_send_stop(void)
>   {
>   	static int cpus_stopped;
> @@ -66,7 +91,9 @@ void crash_smp_send_stop(void)
>   	atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
>   
>   	pr_crit("SMP: stopping secondary CPUs\n");
> -	send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
> +
> +	if (send_nmi_stop_cpu(&mask))
> +		send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
>   
>   	/* Wait up to one second for other CPUs to stop */
>   	timeout = USEC_PER_SEC;
> diff --git a/drivers/firmware/riscv/sse_nmi.c b/drivers/firmware/riscv/sse_nmi.c
> index 2c1eaea2bbabc..152d787075345 100644
> --- a/drivers/firmware/riscv/sse_nmi.c
> +++ b/drivers/firmware/riscv/sse_nmi.c
> @@ -4,13 +4,16 @@
>   
>   #include <linux/nmi.h>
>   #include <linux/riscv_sbi_sse.h>
> +#include <linux/sse_nmi.h>
>   #include <linux/sysctl.h>
>   
> +#include <asm/crash.h>
>   #include <asm/irq_regs.h>
>   #include <asm/sbi.h>
>   
>   int unknown_nmi_panic;
>   static struct sse_event *unknown_nmi_evt;
> +static struct sse_event *crash_nmi_evt;
>   static struct ctl_table_header *unknown_nmi_sysctl_header;
>   
>   static int __init setup_unknown_nmi_panic(char *str)
> @@ -32,6 +35,12 @@ const struct ctl_table unknown_nmi_table[] = {
>   	},
>   };
>   
> +static inline struct sbiret sbi_sse_ecall(int fid, unsigned long arg0,
> +					  unsigned long arg1)
> +{
> +	return sbi_ecall(SBI_EXT_SSE, fid, arg0, arg1, 0, 0, 0, 0);
> +}
> +
>   static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
>   {
>   	pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id());
> @@ -73,9 +82,69 @@ static int unknown_nmi_init(void)
>   	return ret;
>   }
>   
> +#ifdef CONFIG_KEXEC_CORE
> +int carsh_nmi_stop_cpu(unsigned int cpu)
> +{
> +	unsigned int hart_id = cpuid_to_hartid_map(cpu);
> +	u32 evt = SBI_SSE_EVENT_LOCAL_CRASH_NMI;
> +	struct sbiret ret;
> +
> +	ret = sbi_sse_ecall(SBI_SSE_EVENT_INJECT, evt, hart_id);
> +	if (ret.error) {
> +		pr_err("Failed to signal event %x, error %ld\n", evt, ret.error);
> +		return sbi_err_map_linux_errno(ret.error);
> +	}
> +
> +	return 0;
> +}
> +
> +static int crash_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
> +{
> +	cpu_crash_stop(smp_processor_id(), regs);
> +
> +	return 0;
> +}
> +
> +static int crash_nmi_init(void)
> +{
> +	int ret;
> +
> +	crash_nmi_evt = sse_event_register(SBI_SSE_EVENT_LOCAL_CRASH_NMI, 0,
> +				 crash_nmi_handler, NULL);
> +	if (IS_ERR(crash_nmi_evt))
> +		return PTR_ERR(crash_nmi_evt);
> +
> +	ret = sse_event_enable(crash_nmi_evt);
> +	if (ret) {
> +		sse_event_unregister(crash_nmi_evt);
> +		return ret;
> +	}
> +
> +	pr_info("Using SSE for crash NMI event delivery\n");
> +
> +	return 0;
> +}
> +#endif
> +
>   static int __init sse_nmi_init(void)
>   {
> -	return unknown_nmi_init();
> +	int ret;
> +
> +	ret = unknown_nmi_init();
> +	if (ret) {
> +		pr_err("Unknown_nmi_init failed with error %d\n", ret);
> +		return ret;
> +	}
> +
> +#ifdef CONFIG_KEXEC_CORE
> +	ret = crash_nmi_init();
> +	if (ret) {
> +		pr_err("Crash_nmi_init failed with error %d\n", ret);
> +		return ret;
> +	}
> +#endif
> +
> +	return 0;
>   }
>   
>   late_initcall(sse_nmi_init);
> diff --git a/include/linux/sse_nmi.h b/include/linux/sse_nmi.h
> new file mode 100644
> index 0000000000000..548a348ac0a46
> --- /dev/null
> +++ b/include/linux/sse_nmi.h
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __LINUX_RISCV_SSE_NMI_H
> +#define __LINUX_RISCV_SSE_NMI_H
> +
> +int carsh_nmi_stop_cpu(unsigned int cpu);
> +
> +#endif

Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU

[Bagas Sanjaya]

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On Thu, Oct 30, 2025 at 01:46:40AM -0700, Atish Patra wrote:
> 1. Invoking SSE on this path may lead to some race conditions if
> interruption is enabled.

What race condition?

Confused...

-- 
An old man doll... just what I always wanted! - Clara

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