From: "Junhui Liu" <junhui.liu@pigmoral.tech>
To: "Brian Masney" <bmasney@redhat.com>,
"Junhui Liu" <junhui.liu@pigmoral.tech>
Cc: "Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>, <linux-clk@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH v3 3/6] clk: anlogic: add cru support for Anlogic DR1V90 SoC
Date: Fri, 19 Dec 2025 16:32:18 +0800 [thread overview]
Message-ID: <DF21Y2Y8FHSY.148HX8VXOFBHV@pigmoral.tech> (raw)
In-Reply-To: <aUSQLB1fmYgQe_Fg@redhat.com>
Hi Brian,
Thanks for your review.
On Fri Dec 19, 2025 at 7:37 AM CST, Brian Masney wrote:
> Hi Junhui,
>
> On Tue, Dec 16, 2025 at 11:39:43AM +0800, Junhui Liu wrote:
>> +static long cru_div_gate_round_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long *prate)
>> +{
>> + struct clk_divider *divider = to_clk_divider(hw);
>> +
>> + return divider_round_rate(hw, rate, prate, divider->table,
>> + divider->width, divider->flags);
>> +}
>
> The round_rate clk op is deprecated and I'm really close to being able
> to remove this from the clk core. Please only use determine_rate()
> below.
Thanks! I will remove the round_rate() implementation and use
determine_rate() only.
>
>> +static int cru_div_gate_determine_rate(struct clk_hw *hw,
>> + struct clk_rate_request *req)
>> +{
>> + struct cru_div_gate *div_gate = hw_to_cru_div_gate(hw);
>> + struct clk_divider *divider = &div_gate->divider;
>> + unsigned long maxdiv, mindiv;
>> + int div = 0;
>> +
>> + maxdiv = clk_div_mask(divider->width) + 1;
>> + mindiv = div_gate->min + 1;
>> +
>> + div = DIV_ROUND_UP_ULL(req->best_parent_rate, req->rate);
>> + div = div > maxdiv ? maxdiv : div;
>> + div = div < mindiv ? mindiv : div;
>> +
>> + req->rate = DIV_ROUND_UP_ULL(req->best_parent_rate, div);
>> +
>> + return 0;
>> +}
>
> [snip]
>
>> +const struct clk_ops dr1_cru_div_gate_ops = {
>> + .enable = cru_div_gate_enable,
>> + .disable = cru_div_gate_disable,
>> + .is_enabled = cru_div_gate_is_enabled,
>> + .recalc_rate = cru_div_gate_recalc_rate,
>> + .round_rate = cru_div_gate_round_rate,
>> + .determine_rate = cru_div_gate_determine_rate,
>
> When round_rate() and determine_rate() are both defined in the provider,
> only the determine_rate() will be used. Just drop your round_rate()
> implementation.
You're right, it's redundant here. I'll remove it in the next version.
>
> I didn't look into anything else on this patch. This showed up on my
> search for new implementations.
>
> Brian
--
Best regards,
Junhui Liu
next prev parent reply other threads:[~2025-12-19 8:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-16 3:39 [PATCH v3 0/6] clk/reset: anlogic: add support for DR1V90 SoC Junhui Liu
2025-12-16 3:39 ` [PATCH v3 1/6] clk: correct clk_div_mask() return value for width == 32 Junhui Liu
2025-12-22 18:48 ` Brian Masney
2025-12-16 3:39 ` [PATCH v3 2/6] dt-bindings: clock: add Anlogic DR1V90 CRU Junhui Liu
2025-12-16 3:39 ` [PATCH v3 3/6] clk: anlogic: add cru support for Anlogic DR1V90 SoC Junhui Liu
2025-12-18 23:37 ` Brian Masney
2025-12-19 8:32 ` Junhui Liu [this message]
2025-12-16 3:39 ` [PATCH v3 4/6] reset: anlogic: add support for Anlogic DR1V90 resets Junhui Liu
2025-12-16 3:39 ` [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90 Junhui Liu
2025-12-16 3:39 ` [PATCH v3 6/6] MAINTAINERS: Add entry for Anlogic DR1V90 SoC drivers Junhui Liu
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