From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86E432FFDEC for ; Tue, 6 Jan 2026 20:25:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767731144; cv=none; b=N46nySnElF52uslM8zN6KCm5qdHKYa8tgarLRJj5r1aH6DbD3D+p7AOrLnh29h8ydaBhc9mpvCNwrFkGKSZ5X0rYC3tCVjOoDTeCAA64QMF1F3Q99GkspIFndbPxx+V2FoOlhps+V93/SH+a1dl1XqckZDw+mZBg6e4ZJAhxfUM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767731144; c=relaxed/simple; bh=4VJiQTxa7PtrsDjtxpG4+7kDp0RAbcK3Jts1P7QEKlc=; h=Mime-Version:Content-Type:Date:Message-Id:Cc:Subject:From:To: References:In-Reply-To; b=U1f/03xpzipnpmxL5IEHb3bS4BG97/g5WkdD+9UoPMHkD+lhfE0kMMptWo9x1fRS8pdntMX9LgYe/WiqtqucEj/VV9vEJmoEuhWqTdaFzHvH5ELZW2G5/IaXfEmBlzaMFsNs9SD8F9z8fSG91esCZxpddif8OtDY4BPWNyOb75Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=B4sVgwLT; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="B4sVgwLT" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-430f57cd471so681082f8f.0 for ; Tue, 06 Jan 2026 12:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1767731139; x=1768335939; darn=vger.kernel.org; h=in-reply-to:references:to:from:subject:cc:message-id:date :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=InpRCJH4Ts9JhFLpum27mQzhd0pB52v3DryP5nM70Ok=; b=B4sVgwLTqCaGYDe0ZE0CJO8HhfcDqMvPsoOD6DKmrnPqXHu7+T4Agj26RwT4M79mYc UQY3vUY65V1/kIu9FX9+/a+sHdd0VjhKUQZ0YPB+mfQS97/GEMPNqJ2NTTbTM3IH/tew 70n5aG3tj+qb2La+pNIJ+MGhFCxvtTRI9IGv4sdLulzCyGx9nhixMOBee0gSXrPupMr2 9Ntf8tk8nWN4FrqTmIE3JRHz7oKOHj32TYCDmObuMCwdiKk31cunhWmQ8mV19z0/lj2H uTNlGGtBCPfFVnuvdzElhyC3WDNotocFM6k8HrEbquSg9Q1Lv724SjtCFGhgu6l8qkqC 6cIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767731139; x=1768335939; h=in-reply-to:references:to:from:subject:cc:message-id:date :mime-version:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=InpRCJH4Ts9JhFLpum27mQzhd0pB52v3DryP5nM70Ok=; b=AQSOOfpr7JSCnKSZ3aJg5Vq7EpHi53cpLAhU9rwZFgVevoedSVB0vd7w0uUnCk4yb6 au9EGqLuw7oHuoTMyWcvel/azpovCCgxRHeNnpft0g5/bz2qjgJhNhB2KhX7iTloPYVK xIur39jglmT6CyOuxwjE2L2HAZYXkXKhgmYBNNoOSCZFdcCHz6oNGg+kL3Q6uwtMJS2p aNdOKyZ+lxeFGI/+BVQUuky5L2VKSDQT0HMIxvYNZ7cMh+ue6drYbvxoUacbx8OTzgcg XPKy/Hn8HPt3mxGbkRCjpxiOrYAG9LU9kR7n22kA6SDJMheXWbCFgSwFEqccUC1ViuZr MsRA== X-Forwarded-Encrypted: i=1; AJvYcCUCUqFCwWqnigZBxGWRGoZu4DemPoIhoyUpgrs70WXbPKUruPTDbsDq4WDWK0XHkLivyKZIbqjuAVD0VWo=@vger.kernel.org X-Gm-Message-State: AOJu0YwioqrwlaxQLpvsF2okwreNNZF+qnfGcQg0h4TbEPq+1stmQnf8 i0BuEgLUX5fzzJ77Xfmn3ZvqGYbpf4uGIKPDYm+mRP+spHGBUanOFBp29oli4X6iiQU= X-Gm-Gg: AY/fxX7HSmRgPJrLF1DLjw0jmuQMCe6e2VDqRXTP7kkxy+GDeCt+pd3PFg9L4FWhF8V IMQ2898tXfqsQkHhsGR92lwao7gURCLBnzmZV5+Mz9bhtjui0ZmsQ8ymuQLFnWiBNa+cTnLkLlL BIMe65oa5gwpTWWAwbFwKJAP/QTpPDaCJhJ40yvo6VmGbkKQh51bU/wUpuyPfwPZxvi7drXtZ6G EhFUy+xpZcw7WnB6T8+8q7ZXjYyyBTq0Mwovh3wO3KEWPgjR6hXgZoKUv1gsC488vbllDHLTglu nLNapYF/cL+B6qCk50FEW0aeTtovbqP2Z0EBEF0tpnCIOtoI0LoeYhXtlD//lHSe2bo/ErQVPMt kexG0LzXo+rYJ4RA3tVDgL+34tjDymkY0jn5fYQHcDNXW+xnxTd/9MmqaxOgYvGmTZyHDe3uaeO Lm6/XS X-Google-Smtp-Source: AGHT+IF2eFD4qqiNSfi8TwKianKXVDZdxvtrCaDoHkxKfUBqtaeXICo1xMsMfKjQgmu0rURXgO0oVw== X-Received: by 2002:a05:6000:2512:b0:431:a50:6e97 with SMTP id ffacd0b85a97d-432c374ff11mr435166f8f.34.1767731139002; Tue, 06 Jan 2026 12:25:39 -0800 (PST) Received: from localhost ([195.52.160.197]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd5ff0b2sm6200416f8f.42.2026.01.06.12.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jan 2026 12:25:37 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Type: multipart/signed; boundary=5148a380f6f7e57f68a4497ee98a33d6cccc4f9c818445a72768aefddb6f; micalg=pgp-sha512; protocol="application/pgp-signature" Date: Tue, 06 Jan 2026 21:25:29 +0100 Message-Id: Cc: "Vishal Mahaveer" , "Kevin Hilman" , "Dhruva Gole" , "Sebin Francis" , "Kendall Willis" , "Akashdeep Kaur" , , , Subject: Re: [PATCH] arm64: dts: ti: k3-am62a7-sk: Disable mmc Schmitt Trigger From: "Markus Schneider-Pargmann" To: "Alexander Sverdlin" , "Markus Schneider-Pargmann (TI.com)" , "Nishanth Menon" , "Vignesh Raghavendra" , "Tero Kristo" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" X-Mailer: aerc 0.21.0 References: <20260106-topic-am62a-mmc-pinctrl-v6-19-next-v1-1-1190ac29aadb@baylibre.com> <979eb1054dbe116c2c8bb9920e94e3a93db5346c.camel@gmail.com> In-Reply-To: <979eb1054dbe116c2c8bb9920e94e3a93db5346c.camel@gmail.com> --5148a380f6f7e57f68a4497ee98a33d6cccc4f9c818445a72768aefddb6f Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Hi Alexander, On Tue Jan 6, 2026 at 6:25 PM CET, Alexander Sverdlin wrote: > Hi Markus, > > I'm sorry my patch has caused regression for your use-case! > > I think we would need to discuss this with TI via our FAE, because the ch= ange > in question has both been discussed with former FAE and the technical tea= m > behind, and adopted in TI SDK. > > Or have you already discused this with corresponding TI HW team? > > Which hardware is affected, is it the official SK-AM62A-LP? > Is MMC2 the SD-card? I only tested my am62a board on u-boot v2026.01. It is a SK-AM62A-LP. MMC2 is the SD-card and mmc1 in the devicetree. I am using u-boot's am62ax_evm_r5_defconfig and am62ax_evm_a53_defconfig as defconfigs. > > On Tue, 2026-01-06 at 17:22 +0100, Markus Schneider-Pargmann (TI.com) wro= te: >> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled >> u-boot SPL is not able to read u-boot from mmc: >>=20 >> =C2=A0=C2=A0=C2=A0 Trying to boot from MMC2 >> =C2=A0=C2=A0=C2=A0 Error reading cluster >> =C2=A0=C2=A0=C2=A0 spl_load_image_fat: error reading image u-boot.img, e= rr - -22 >> =C2=A0=C2=A0=C2=A0 Error: -22 >> =C2=A0=C2=A0=C2=A0 SPL: Unsupported Boot Device! >> =C2=A0=C2=A0=C2=A0 SPL: failed to boot from all boot devices >> =C2=A0=C2=A0=C2=A0 ### ERROR ### Please RESET the board ### >>=20 >> I bisected this issue between u-boot v2025.10 and v2026.01 and found the >> devicetree merge to be the problem. At a closer look I found the >> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL >> failure to read from mmc. >>=20 >> Fixes: 5b272127884b ("arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger= by default") >> Signed-off-by: Markus Schneider-Pargmann (TI.com) >> --- >> =C2=A0arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 36 ++++++++++++++++-----= ------------ >> =C2=A01 file changed, 18 insertions(+), 18 deletions(-) >>=20 >> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/d= ts/ti/k3-am62a7-sk.dts >> index e99bdbc2e0cbdf858f1631096f9c2a086191bab3..9129045c8bbd3a83dba6ff6f= 2148a3624b91b546 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts >> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts >> @@ -315,30 +315,30 @@ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) = GPMC0_CSn3.I2C2_SDA */ >> =C2=A0 >> =C2=A0 main_mmc0_pins_default: main-mmc0-default-pins { >> =C2=A0 pinctrl-single,pins =3D < >> - AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ >> - AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */ >> - AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ > > according to datasheet, MMC0_CLK should have address 0x218 and it's the b= all AB7. > MMC0_CLKLB is not present in the datasheet and AB1 is actually VSS. 0x21C= address > is not documented. > > Something is not right here... > > OK, grepping TRM for CLKLB, one can conclude that 0x21c is actually MMC0_= CLKLB. > > Could you please try to modify 0x21c address only? Does it solve the boot= problem? > >> - AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ >> - AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ >> - AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ >> - AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ >> - AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ >> - AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ >> - AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ >> - AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ > > All the rest actually have ST enabled on PoR according to TRM and I suppo= se BootROM > would have had hard times booting from the affected MMC device if it woul= d not be > the correct setting? > >> + AM62AX_IOPAD(0x220, PIN_INPUT_NOST, 0) /* (Y3) MMC0_CMD */ >> + AM62AX_IOPAD(0x218, PIN_INPUT_NOST, 0) /* (AB1) MMC0_CLKLB */ >> + AM62AX_IOPAD(0x21c, PIN_INPUT_NOST, 0) /* (AB1) MMC0_CLK */ >> + AM62AX_IOPAD(0x214, PIN_INPUT_NOST, 0) /* (AA2) MMC0_DAT0 */ >> + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP_NOST, 0) /* (AA1) MMC0_DAT1 */ >> + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP_NOST, 0) /* (AA3) MMC0_DAT2 */ >> + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP_NOST, 0) /* (Y4) MMC0_DAT3 */ >> + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP_NOST, 0) /* (AB2) MMC0_DAT4 */ >> + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP_NOST, 0) /* (AC1) MMC0_DAT5 */ >> + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP_NOST, 0) /* (AD2) MMC0_DAT6 */ >> + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP_NOST, 0) /* (AC2) MMC0_DAT7 */ >> =C2=A0 >; >> =C2=A0 bootph-all; >> =C2=A0 }; >> =C2=A0 >> =C2=A0 main_mmc1_pins_default: main-mmc1-default-pins { >> =C2=A0 pinctrl-single,pins =3D < >> - AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ >> - AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ >> - AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ >> - AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ >> - AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ >> - AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ >> - AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ > > All of these have ST enabled on PoR, according to TRM. > >> + AM62AX_IOPAD(0x23c, PIN_INPUT_NOST, 0) /* (A21) MMC1_CMD */ >> + AM62AX_IOPAD(0x234, PIN_INPUT_NOST, 0) /* (B22) MMC1_CLK */ >> + AM62AX_IOPAD(0x230, PIN_INPUT_NOST, 0) /* (A22) MMC1_DAT0 */ >> + AM62AX_IOPAD(0x22c, PIN_INPUT_NOST, 0) /* (B21) MMC1_DAT1 */ >> + AM62AX_IOPAD(0x228, PIN_INPUT_NOST, 0) /* (C21) MMC1_DAT2 */ >> + AM62AX_IOPAD(0x224, PIN_INPUT_NOST, 0) /* (D22) MMC1_DAT3 */ >> + AM62AX_IOPAD(0x240, PIN_INPUT_NOST, 0) /* (D17) MMC1_SDCD */ My board is setup to boot from SD card for easier u-boot testing. So only the mmc1 is relevant for my setup. I just tested which pins need NOST here for the boot to work, all DAT pins need the NOST variants, otherwise it does not boot here. Not sure if this is just my board or it fails on other boards as well. Best Markus --5148a380f6f7e57f68a4497ee98a33d6cccc4f9c818445a72768aefddb6f Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iKMEABYKAEsWIQSJYVVm/x+5xmOiprOFwVZpkBVKUwUCaV1vuRsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMSwyLDIRHG1zcEBiYXlsaWJyZS5jb20ACgkQhcFWaZAVSlNB 7QEA+fNdxGsI7MEgje1RhFzgNhDzAEC+9JsbotuUWDJyF44BAKqWmNM7DgUAdP6H 2khSJFPWlKuRNiBljEo4WVwfei4C =32OF -----END PGP SIGNATURE----- --5148a380f6f7e57f68a4497ee98a33d6cccc4f9c818445a72768aefddb6f--