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Hopper/Blackwell+ have a larger width, so do an > early read of boot42, in order to pick the correct value. > > Signed-off-by: John Hubbard > --- > drivers/gpu/nova-core/driver.rs | 33 +++++++++++++++++---------------- > drivers/gpu/nova-core/gpu.rs | 29 ++++++++++++++++++++++++++++- > 2 files changed, 45 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driv= er.rs > index d91bbc50cde7..3179a4d47af4 100644 > --- a/drivers/gpu/nova-core/driver.rs > +++ b/drivers/gpu/nova-core/driver.rs > @@ -4,8 +4,10 @@ > auxiliary, > c_str, > device::Core, > - dma::Device, > - dma::DmaMask, > + dma::{ > + Device, > + DmaMask, // > + }, > pci, > pci::{ > Class, > @@ -17,7 +19,10 @@ > sync::Arc, // > }; > =20 > -use crate::gpu::Gpu; > +use crate::gpu::{ > + read_architecture, > + Gpu, // > +}; > =20 > #[pin_data] > pub(crate) struct NovaCore { > @@ -28,14 +33,6 @@ pub(crate) struct NovaCore { > =20 > const BAR0_SIZE: usize =3D SZ_16M; > =20 > -// For now we only support Ampere which can use up to 47-bit DMA address= es. > -// > -// TODO: Add an abstraction for this to support newer GPUs which may sup= port > -// larger DMA addresses. Limiting these GPUs to smaller address widths w= on't > -// have any adverse affects, unless installed on systems which require l= arger > -// DMA addresses. These systems should be quite rare. > -const GPU_DMA_BITS: u32 =3D 47; > - > pub(crate) type Bar0 =3D pci::Bar; > =20 > kernel::pci_device_table!( > @@ -73,11 +70,6 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInf= o) -> Result pdev.enable_device_mem()?; > pdev.set_master(); > =20 > - // SAFETY: No concurrent DMA allocations or mappings can be made= because > - // the device is still being probed and therefore isn't being us= ed by > - // other threads of execution. > - unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::())? }; > - > let devres_bar =3D Arc::pin_init( > pdev.iomap_region_sized::(0, c_str!("nova-core/ba= r0")), > GFP_KERNEL, > @@ -88,6 +80,15 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInf= o) -> Result let bar_clone =3D Arc::clone(&devres_bar); > let bar =3D bar_clone.access(pdev.as_ref())?; > =20 > + // Read the GPU architecture early to determine the correct DMA = address width. > + // Hopper/Blackwell+ support 52-bit DMA addresses, earlier archi= tectures use 47-bit. > + let arch =3D read_architecture(bar)?; > + > + // SAFETY: No concurrent DMA allocations or mappings can be made= because > + // the device is still being probed and therefore isn't being us= ed by > + // other threads of execution. > + unsafe { pdev.dma_set_mask_and_coherent(DmaMask::try_new(arch.dm= a_addr_bits())?)? }; > + > let this =3D KBox::pin_init( > try_pin_init!(Self { > gpu <- Gpu::new(pdev, devres_bar, bar), > diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs > index c21ce91924f5..624bbc2a54e8 100644 > --- a/drivers/gpu/nova-core/gpu.rs > +++ b/drivers/gpu/nova-core/gpu.rs > @@ -102,7 +102,7 @@ fn try_from(value: u32) -> Result = { > }); > =20 > impl Chipset { > - pub(crate) fn arch(&self) -> Architecture { > + pub(crate) const fn arch(&self) -> Architecture { > match self { > Self::TU102 | Self::TU104 | Self::TU106 | Self::TU117 | Self= ::TU116 =3D> { > Architecture::Turing > @@ -155,6 +155,19 @@ pub(crate) enum Architecture { > Blackwell =3D 0x1b, > } > =20 > +impl Architecture { > + /// Returns the number of DMA address bits supported by this archite= cture. > + /// > + /// Hopper and Blackwell support 52-bit DMA addresses, while earlier= architectures > + /// (Turing, Ampere, Ada) support 47-bit DMA addresses. > + pub(crate) const fn dma_addr_bits(&self) -> u32 { How about just return `DmaMask` from here? This get rids of the fallible constructor call of `DmaMask`. > + match self { > + Self::Turing | Self::Ampere | Self::Ada =3D> 47, > + Self::Hopper | Self::Blackwell =3D> 52, > + } > + } > +} > + > impl TryFrom for Architecture { > type Error =3D Error; > =20 > @@ -203,6 +216,20 @@ pub(crate) struct Spec { > revision: Revision, > } > =20 > +/// Reads the GPU architecture from BAR0 registers. > +/// > +/// This is a lightweight check used early in probe to determine the cor= rect DMA address width > +/// before the full [`Spec`] is constructed. > +pub(crate) fn read_architecture(bar: &Bar0) -> Result { > + let boot0 =3D regs::NV_PMC_BOOT_0::read(bar); > + > + if boot0.is_older_than_fermi() { > + return Err(ENODEV); > + } > + > + regs::NV_PMC_BOOT_42::read(bar).architecture() Can this just be `Spec::new`? Best, Gary > +} > + > impl Spec { > fn new(dev: &device::Device, bar: &Bar0) -> Result { > // Some brief notes about boot0 and boot42, in chronological ord= er: