Re: [PATCH v8 4/5] rust: pci: add config space read/write support

Danilo Krummrich
2026-01-13T19:48:32Z

On Tue Jan 13, 2026 at 10:22 AM CET, Zhi Wang wrote:
> diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
> index 82e128431f08..f373413e8a84 100644
> --- a/rust/kernel/pci.rs
> +++ b/rust/kernel/pci.rs
> @@ -40,7 +40,10 @@
> ClassMask,
> Vendor, //
> };
> -pub use self::io::Bar;
> +pub use self::io::{
> + Bar,
> + ConfigSpace, //
> +};
> pub use self::irq::{
> IrqType,
> IrqTypes,
> @@ -331,6 +334,30 @@ fn as_raw(&self) -> *mut bindings::pci_dev {
> }
> }
>
> +/// Represents the size of a PCI configuration space.
> +///
> +/// PCI devices can have either a *normal* (legacy) configuration space of 256 bytes,
> +/// or an *extended* configuration space of 4096 bytes as defined in the PCI Express
> +/// specification.
> +#[repr(usize)]
> +pub enum ConfigSpaceSize {
> + /// 256-byte legacy PCI configuration space.
> + Normal = 256,
> +
> + /// 4096-byte PCIe extended configuration space.
> + Extended = 4096,
> +}
> +
> +impl ConfigSpaceSize {
> + /// Get the raw value of this enum.
> + #[inline(always)]
> + pub const fn as_raw(self) -> usize {
> + // CAST: PCI configuration space size is at most 4096 bytes, so the value always fits
> + // within `usize` without truncation or sign change.
> + self as usize
> + }
> +}

Please move this to rust/kernel/pci/io.rs as well.

> +
> impl Device {
> /// Returns the PCI vendor ID as [`Vendor`].
> ///
> @@ -427,6 +454,20 @@ pub fn pci_class(&self) -> Class {
> // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
> Class::from_raw(unsafe { (*self.as_raw()).class })
> }
> +
> + /// Returns the size of configuration space.
> + fn cfg_size(&self) -> Result<ConfigSpaceSize> {
> + // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
> + let size = unsafe { (*self.as_raw()).cfg_size };
> + match size {
> + 256 => Ok(ConfigSpaceSize::Normal),
> + 4096 => Ok(ConfigSpaceSize::Extended),
> + _ => {
> + debug_assert!(false);
> + Err(EINVAL)
> + }
> + }
> + }

Same here.

> }
>
> impl Device<device::Core> {
> diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs
> index e3377397666e..c8741f0080ec 100644
> --- a/rust/kernel/pci/io.rs
> +++ b/rust/kernel/pci/io.rs
> @@ -2,12 +2,19 @@
>
> //! PCI memory-mapped I/O infrastructure.
>
> -use super::Device;
> +use super::{
> + ConfigSpaceSize,
> + Device, //
> +};
> use crate::{
> bindings,
> device,
> devres::Devres,
> io::{
> + define_read,
> + define_write,
> + IoBase,
> + IoKnownSize,
> Mmio,
> MmioRaw, //
> },
> @@ -16,6 +23,101 @@
> };
> use core::ops::Deref;
>
> +/// The PCI configuration space of a device.
> +///
> +/// Provides typed read and write accessors for configuration registers
> +/// using the standard `pci_read_config_*` and `pci_write_config_*` helpers.
> +///
> +/// The generic const parameter `SIZE` can be used to indicate the
> +/// maximum size of the configuration space (e.g. 256 bytes for legacy,
> +/// 4096 bytes for extended config space).

Let's refer to ConfigSpaceSize instead.

> +pub struct ConfigSpace<'a, const SIZE: usize = { ConfigSpaceSize::Extended as usize }> {
> + pub(crate) pdev: &'a Device<device::Bound>,
> +}