Re: [PATCH v8 4/5] rust: pci: add config space read/write support

Zhi Wang
2026-01-15T08:15:55Z

On Tue, 13 Jan 2026 11:22:51 +0200
Zhi Wang <zhiw@nvidia.com> wrote:

Thanks, I will re-spin this today.

> Drivers might need to access PCI config space for querying capability
> structures and access the registers inside the structures.
>
> For Rust drivers need to access PCI config space, the Rust PCI
> abstraction needs to support it in a way that upholds Rust's safety
> principles.
>
> Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe
> accessors for PCI config space. The new type implements the `Io` trait to
> share offset validation and bound-checking logic with others.
>
> Cc: Alexandre Courbot <acourbot@nvidia.com>
> Cc: Danilo Krummrich <dakr@kernel.org>
> Cc: Joel Fernandes <joelagnelf@nvidia.com>
> Signed-off-by: Zhi Wang <zhiw@nvidia.com>
> ---
> rust/kernel/pci.rs | 43 ++++++++++++++-
> rust/kernel/pci/io.rs | 118 +++++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 159 insertions(+), 2 deletions(-)
>
> diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
> index 82e128431f08..f373413e8a84 100644
> --- a/rust/kernel/pci.rs
> +++ b/rust/kernel/pci.rs
> @@ -40,7 +40,10 @@
> ClassMask,
> Vendor, //
> };
> -pub use self::io::Bar;
> +pub use self::io::{
> + Bar,
> + ConfigSpace, //
> +};
> pub use self::irq::{
> IrqType,
> IrqTypes,
> @@ -331,6 +334,30 @@ fn as_raw(&self) -> *mut bindings::pci_dev {
> }
> }
>
> +/// Represents the size of a PCI configuration space.
> +///
> +/// PCI devices can have either a *normal* (legacy) configuration space
> of 256 bytes, +/// or an *extended* configuration space of 4096 bytes as
> defined in the PCI Express +/// specification.
> +#[repr(usize)]
> +pub enum ConfigSpaceSize {
> + /// 256-byte legacy PCI configuration space.
> + Normal = 256,
> +
> + /// 4096-byte PCIe extended configuration space.
> + Extended = 4096,
> +}
> +
> +impl ConfigSpaceSize {
> + /// Get the raw value of this enum.
> + #[inline(always)]
> + pub const fn as_raw(self) -> usize {
> + // CAST: PCI configuration space size is at most 4096 bytes, so
> the value always fits
> + // within `usize` without truncation or sign change.
> + self as usize
> + }
> +}
> +
> impl Device {
> /// Returns the PCI vendor ID as [`Vendor`].
> ///
> @@ -427,6 +454,20 @@ pub fn pci_class(&self) -> Class {
> // SAFETY: `self.as_raw` is a valid pointer to a `struct
> pci_dev`. Class::from_raw(unsafe { (*self.as_raw()).class })
> }
> +
> + /// Returns the size of configuration space.
> + fn cfg_size(&self) -> Result<ConfigSpaceSize> {
> + // SAFETY: `self.as_raw` is a valid pointer to a `struct
> pci_dev`.
> + let size = unsafe { (*self.as_raw()).cfg_size };
> + match size {
> + 256 => Ok(ConfigSpaceSize::Normal),
> + 4096 => Ok(ConfigSpaceSize::Extended),
> + _ => {
> + debug_assert!(false);
> + Err(EINVAL)
> + }
> + }
> + }
> }
>
> impl Device<device::Core> {
> diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs
> index e3377397666e..c8741f0080ec 100644
> --- a/rust/kernel/pci/io.rs
> +++ b/rust/kernel/pci/io.rs
> @@ -2,12 +2,19 @@
>
> //! PCI memory-mapped I/O infrastructure.
>
> -use super::Device;
> +use super::{
> + ConfigSpaceSize,
> + Device, //
> +};
> use crate::{
> bindings,
> device,
> devres::Devres,
> io::{
> + define_read,
> + define_write,
> + IoBase,
> + IoKnownSize,
> Mmio,
> MmioRaw, //
> },
> @@ -16,6 +23,101 @@
> };
> use core::ops::Deref;
>
> +/// The PCI configuration space of a device.
> +///
> +/// Provides typed read and write accessors for configuration registers
> +/// using the standard `pci_read_config_*` and `pci_write_config_*`
> helpers. +///
> +/// The generic const parameter `SIZE` can be used to indicate the
> +/// maximum size of the configuration space (e.g. 256 bytes for legacy,
> +/// 4096 bytes for extended config space).
> +pub struct ConfigSpace<'a, const SIZE: usize = {
> ConfigSpaceSize::Extended as usize }> {
> + pub(crate) pdev: &'a Device<device::Bound>,
> +}
> +
> +/// Internal helper macros used to invoke C PCI configuration space
> read functions. +///
> +/// This macro is intended to be used by higher-level PCI configuration
> space access macros +/// (define_read) and provides a unified expansion
> for infallible vs. fallible read semantics. It +/// emits a direct call
> into the corresponding C helper and performs the required cast to the
> Rust +/// return type. +///
> +/// # Parameters
> +///
> +/// * `$c_fn` – The C function performing the PCI configuration space
> write. +/// * `$self` – The I/O backend object.
> +/// * `$ty` – The type of the value to read.
> +/// * `$addr` – The PCI configuration space offset to read.
> +///
> +/// This macro does not perform any validation; all invariants must be
> upheld by the higher-level +/// abstraction invoking it.
> +macro_rules! call_config_read {
> + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) => {{
> + let mut val: $ty = 0;
> + // SAFETY: By the type invariant `$self.pdev` is a valid
> address.
> + // CAST: The offset is cast to `i32` because the C functions
> expect a 32-bit signed offset
> + // parameter. PCI configuration space size is at most 4096
> bytes, so the value always fits
> + // within `i32` without truncation or sign change.
> + // Return value from C function is ignored in infallible
> accessors.
> + let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr
> as i32, &mut val) };
> + val
> + }};
> +}
> +
> +/// Internal helper macros used to invoke C PCI configuration space
> write functions. +///
> +/// This macro is intended to be used by higher-level PCI configuration
> space access macros +/// (define_write) and provides a unified expansion
> for infallible vs. fallible read semantics. It +/// emits a direct call
> into the corresponding C helper and performs the required cast to the
> Rust +/// return type. +///
> +/// # Parameters
> +///
> +/// * `$c_fn` – The C function performing the PCI configuration space
> write. +/// * `$self` – The I/O backend object.
> +/// * `$ty` – The type of the written value.
> +/// * `$addr` – The configuration space offset to write.
> +/// * `$value` – The value to write.
> +///
> +/// This macro does not perform any validation; all invariants must be
> upheld by the higher-level +/// abstraction invoking it.
> +macro_rules! call_config_write {
> + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr,
> $value:expr) => {
> + // SAFETY: By the type invariant `$self.pdev` is a valid
> address.
> + // CAST: The offset is cast to `i32` because the C functions
> expect a 32-bit signed offset
> + // parameter. PCI configuration space size is at most 4096
> bytes, so the value always fits
> + // within `i32` without truncation or sign change.
> + // Return value from C function is ignored in infallible
> accessors.
> + let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr
> as i32, $value) };
> + };
> +}
> +
> +impl<'a, const SIZE: usize> IoBase for ConfigSpace<'a, SIZE> {
> + const MIN_SIZE: usize = SIZE;
> +
> + /// Returns the base address of the I/O region. It is always 0 for
> configuration space.
> + #[inline]
> + fn addr(&self) -> usize {
> + 0
> + }
> +
> + /// Returns the maximum size of the configuration space.
> + #[inline]
> + fn maxsize(&self) -> usize {
> + self.pdev.cfg_size().map_or(0, |v| v as usize)
> + }
> +}
> +
> +impl<'a, const SIZE: usize> IoKnownSize for ConfigSpace<'a, SIZE> {
> + define_read!(infallible, read8,
> call_config_read(pci_read_config_byte) -> u8);
> + define_read!(infallible, read16,
> call_config_read(pci_read_config_word) -> u16);
> + define_read!(infallible, read32,
> call_config_read(pci_read_config_dword) -> u32); +
> + define_write!(infallible, write8,
> call_config_write(pci_write_config_byte) <- u8);
> + define_write!(infallible, write16,
> call_config_write(pci_write_config_word) <- u16);
> + define_write!(infallible, write32,
> call_config_write(pci_write_config_dword) <- u32); +}
> +
> /// A PCI BAR to perform I/O-Operations on.
> ///
> /// I/O backend assumes that the device is little-endian and will
> automatically @@ -144,4 +246,18 @@ pub fn iomap_region<'a>(
> ) -> impl PinInit<Devres<Bar>, Error> + 'a {
> self.iomap_region_sized::<0>(bar, name)
> }
> +
> + /// Return an initialized config space object.
> + pub fn config_space<'a>(
> + &'a self,
> + ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Normal.as_raw() }>> {
> + Ok(ConfigSpace { pdev: self })
> + }
> +
> + /// Return an initialized config space object.
> + pub fn config_space_extended<'a>(
> + &'a self,
> + ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Extended.as_raw()
> }>> {
> + Ok(ConfigSpace { pdev: self })
> + }
> }