From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59BC938A9B9; Tue, 20 Jan 2026 10:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768903946; cv=none; b=G8FLMlR3MaqO+OxKnOpfGmj9Z4bKBVd10e3U78yPodIv0STqoc2TPEkPHXlUo6J5O6vuB8k5oS2YLcJW4n2XqAKeRf2+zG3IHAUVzpfWwfZ2rs72kLv6laDfhn2P73qNXQjihjU67w0UsFePy6ItMDnHXNA4M+mBub/JT/bcMEg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768903946; c=relaxed/simple; bh=dxSOR0eN/vdhFUeOV8fumG7yv5nlIzfUzyKHu+4HI9s=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:Cc:To:From: References:In-Reply-To; b=VtSMqxcEqKTb79xUduJHFFqoEfTVwrFyzv1scUu3cMTcFdwvuwsm3pf1x4AqxymbI7aUD5dginWek8kxD8BWV+KMS3qO6Bb/ATmWvBy3P8BcM++2c94z2m2taeyNPKbpKeC8HqNXCzJ2fQp03UbFGLEZAqSfZRgLtM7Lg8egkn4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YwQ8b5Rx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YwQ8b5Rx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A82EFC16AAE; Tue, 20 Jan 2026 10:12:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768903945; bh=dxSOR0eN/vdhFUeOV8fumG7yv5nlIzfUzyKHu+4HI9s=; h=Date:Subject:Cc:To:From:References:In-Reply-To:From; b=YwQ8b5RxobMJuydC53XBdRhHGFAUumBN0nRrXwCROoSRN85KxTHEoHCSaxpjlwc03 sT6QMXWmboLZwTb8Bhh8gC0fh8i/wajpyhhO8j6A9KSqm8Y6akCTpk0UIk93kPWnRs EjajSiRpgmhhqF5eDXcp1bH4WT9vw0giZGpnWAd7ofEDM+5Fyw6bCfdx9Mr3301t+t 9M/zHZCyz11yN2GkTivHuU3dVKG61ZAFGMh0vrhkAoIysTTNrP4lCTXB1W6BHkJZXD 7HutSVlrgR8OauVpm4ccy+mhiySbLLoRqLydhmZCG3gI/q8uzW/wfs6V9ONUAhg2pN rXG8JpCCVsLHg== Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 20 Jan 2026 11:12:18 +0100 Message-Id: Subject: Re: [PATCH v10 2/5] rust: io: separate generic I/O helpers from MMIO implementation Cc: "Zhi Wang" , , , , , , , , , , , , , , , , , , , , , , , , , , To: "Alice Ryhl" From: "Danilo Krummrich" References: <20260119202250.870588-1-zhiw@nvidia.com> <20260119202250.870588-3-zhiw@nvidia.com> In-Reply-To: On Tue Jan 20, 2026 at 9:04 AM CET, Alice Ryhl wrote: > On Mon, Jan 19, 2026 at 10:22:44PM +0200, Zhi Wang wrote: > Overall looks good to me. Some comments below: > > I still think it would make sense to have `IoCapable: IoTryCapable`= , > but it's not a big deal. I think with this approach it's not necessary to have this requirement. In practice, most impls will have both, but I think it's a good thing that we = don't have to have an impl even if not used by any driver, i.e. it helps avoiding= dead code. >> + /// Infallible 64-bit read with compile-time bounds check. >> + #[cfg(CONFIG_64BIT)] >> + fn read64(&self, offset: usize) -> u64 >> + #[cfg(CONFIG_64BIT)] >> + fn try_read64(&self, offset: usize) -> Result > > These don't really need cfg(CONFIG_64BIT). You can place that cfg on > impl blocks of IoCapable. If you agree with the above, I can fix this up when applying the series.