From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BD4A368947 for ; Wed, 11 Mar 2026 09:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.206.16.166 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773222963; cv=none; b=fMMz+ArKTYJQyS8zfvk8H8F70/8M6sI+xxE8BctTIGCz53/DbftlNW2Vtls/F+EQfiT6XGPoIL73ByvrRxu1ZZIgTTF90cqu/X7geoFmYprwJbhPKaqET72hvlr6HGhwTHUbnlwiozOXA0nWOPW9Tyq65tL8zLCQ2fOezFCsIgg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773222963; c=relaxed/simple; bh=QM6H1v/vN5/NjkyVHj7osTwLKSPOutwUoZ+s+n8ttLc=; h=Mime-Version:Content-Type:Date:Message-Id:Cc:Subject:From:To: References:In-Reply-To; b=evfq0iHPqQBPU6seKTpgjqWEDpIdyVdXHv9+07Tp4OakKi2EfSYufEKQbY5TWC10xJZ+DUapNwaHF1gvSbz5lez53YHRFYKDRXJeyTse0c2/t+5dIgJiWJazOclf9Hg5Xu64jwrpwrLMZcjjsF/8zaUSBbkcl/CXyX+PQua2OUs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.dev; spf=none smtp.mailfrom=linux.spacemit.com; arc=none smtp.client-ip=54.206.16.166 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.spacemit.com X-QQ-mid: esmtpgz11t1773222844tefda0680 X-QQ-Originating-IP: hVyVvPnZSY/8aV0kXoqb8tsoujiFj3f1URUDvKKAy50= Received: from = ( [120.237.158.181]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 11 Mar 2026 17:54:02 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 17423703683891778313 EX-QQ-RecipientCnt: 9 X-QQ-CSender: troy.mitchell@linux.spacemit.com Sender: troy.mitchell@linux.spacemit.com Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 11 Mar 2026 17:54:02 +0800 Message-Id: Cc: "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , , , Subject: Re: [PATCH RFC] riscv: disable local interrupts and stop other CPUs before restart From: "Troy Mitchell" To: "Troy Mitchell" , "Aurelien Jarno" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260311-v7-0-rc1-rv-dis-int-before-restart-v1-1-bc46b4351cac@linux.dev> In-Reply-To: X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: MSRkgO0tQyp+NozTthkUWuT+MXftymvpedaejj7Wm29SyznRlQsJ0U8/ 7RVxRgkDEOCiVHqgVNDn/PQgZqSeGAEgvUYcMqkiWjIODJ5y/zJQuDHHCH+sXXlaWIT/uke uzWoeAMZPQcR9f2BN9Kw2RNzDx+/BE5B47DA5iS648gQcw0dzDa1eO40eJl8K2Uyp8BNQcn nfvanldbAFIeOg1B0xvse3reCUONs0SM8nb4fL7FJqhrcWMOMAPISrdP5d7mVX3xrBBhGbd FbAHyOeHOzsa7ggLrOG9WuwCAsl1FH5sxVHWvYlgN8NylZLRopNtA8uTfUxRrcnq4zkfqZM GQqNjWlfWBuq1n908DCfB3O3twKytP6cGOLlqieFSEEBF7lhmgjZezQg/8ZkqvQlgFz5KSq ArUACN2DNiXu2Fm3BNnMwP+q4t+u0EQuk6s1Fvd7O5rWeKY3kyPNf4Oao5CRnHF10bPBydP dSh+7P6TFavWJSpCa435KW69r96MosZ9ek7Ogzv1ET3u4qS5+11P5wmlSox8hN/6MWqiFqH Cw39EMlAFhNf7G6fJJdUA4y4BxUN3R+UA95dK18p5hf58tdsyLG/OpKOrDyBBMKudM6RaMV 8WxvwdSj1sKL81OEauGM4agL/K1T8eogGqVUeEZR9cn/YnjhJZmQjUU4dvsom5bCBTaSSHx 8oeYCk0ZDSJsgeNwybBrH3iTjQ6adFbFdZ1ep+mclk+xgAG7OkMEKqgF8of54o0VdHZhoFf BevloFAb5IDTh0c8iyHfpfdL5NnYv6A9IbLc9PTJav3ZzgYQIl2USR6Yi567sPYB75TuHr5 4iQs45Ox0yBdlIqypb/gIGsk9/wA9k+Gz9a14e/eW6NoCGTZCuKansALB06zawZ9qsQDcES biRzODLBMylV8OXVM1I4bzlSnqOB/wQLW9H3+nBmqSLYTUCYjuRvBcHiCj95kNAsRXjaQpF YzVqmeSQzAI6caF4Nfoo0muGqaE9tOuJBaeSFhlXW0r9NdRJ2Gnj9oRNH4e53JnVJ4drK0h 3aR9znMKQuO5VgwKQNDF6yI0zJJ29hCXStoNyxyJI3j0YXRUH5NzvBHobqx50ZVVfDN/e7L SsamT6QoW2NFR2Xly/KsGC8wqBGko+ctGs14tG2kFIZ X-QQ-XMRINFO: MSVp+SPm3vtSI1QTLgDHQqIV1w2oNKDqfg== X-QQ-RECHKSPAM: 0 On Wed Mar 11, 2026 at 5:49 PM CST, Troy Mitchell wrote: > On Wed Mar 11, 2026 at 2:47 PM CST, Aurelien Jarno wrote: >> Hi Troy, >> >> On 2026-03-11 10:51, Troy Mitchell wrote: >>> Currently, the RISC-V implementation of machine_restart() directly call= s >>> do_kernel_restart() without disabling local interrupts or stopping othe= r >>> CPUs. This missing architectural setup causes fatal issues for systems >>> that rely on external peripherals (e.g., I2C PMICs) to execute the syst= em >>> restart when CONFIG_PREEMPT_RCU is enabled. >>>=20 >>> When a restart handler relies on the I2C subsystem, the I2C core checks >>> i2c_in_atomic_xfer_mode() to decide whether to use the sleepable xfer >>> or the polling atomic_xfer. This check evaluates to true if >>> (!preemptible() || irqs_disabled()). >>>=20 >>> During do_kernel_restart(), the restart handlers are invoked via >>> atomic_notifier_call_chain(), which holds an RCU read lock. >>> The behavior diverges based on the preemption model: >>> 1. Under CONFIG_PREEMPT_VOLUNTARY or CONFIG_PREEMPT_NONE, rcu_read_lock= () >>> implicitly disables preemption. preemptible() evaluates to false, an= d >>> the I2C core correctly routes to the atomic, polling transfer path. >>> 2. Under CONFIG_PREEMPT_RCU, rcu_read_lock() does NOT disable preemptio= n. >>> Since machine_restart() left local interrupts enabled, irqs_disabled= () >>> is false, and preempt_count is 0. Consequently, preemptible() evalua= tes >>> to true. >>>=20 >>> As a result, the I2C core falsely assumes a sleepable context and route= s >>> the transfer to the standard master_xfer path. This inevitably triggers= a >>> schedule() call while holding the RCU read lock, resulting in a fatal s= plat: >>> "Voluntary context switch within RCU read-side critical section!" and >>> a system hang. >>>=20 >>> Align RISC-V with other major architectures (e.g., ARM64) by adding >>> local_irq_disable() and smp_send_stop() to machine_restart(). >>> - local_irq_disable() guarantees a strict atomic context, forcing sub- >>> systems like I2C to always fall back to polling mode. >>> - smp_send_stop() ensures exclusive hardware access by quiescing other >>> CPUs, preventing them from holding bus locks (e.g., I2C spinlocks) >>> during the final restart phase. >>>=20 >>> Signed-off-by: Troy Mitchell >>> --- >>> arch/riscv/kernel/reset.c | 5 +++++ >>> 1 file changed, 5 insertions(+) >> >> Thanks. I have been debugging that and it matches my analysis. >> >>> diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c >>> index 912288572226..7a5dcfdc3674 100644 >>> --- a/arch/riscv/kernel/reset.c >>> +++ b/arch/riscv/kernel/reset.c >>> @@ -5,6 +5,7 @@ >>> =20 >>> #include >>> #include >>> +#include >>> =20 >>> static void default_power_off(void) >>> { >>> @@ -17,6 +18,10 @@ EXPORT_SYMBOL(pm_power_off); >>> =20 >>> void machine_restart(char *cmd) >>> { >>> + /* Disable interrupts first */ >>> + local_irq_disable(); >>> + smp_send_stop(); >>> + >>> do_kernel_restart(cmd); >>> while (1); >>> } >>>=20 >> >> I have started to change the power reset driver to call the I2C code=20 >> from a workqueue instead of directly from the notifier call back, but=20 >> that's just papering over the issue. > Since the requirements for i2c_in_atomic() weren't being met, I initially > considered disabling interrupts before the p1 restart code. > > However, I didn't feel that was a generic enough solution, so I looked in= to > the architecture-level implementation. That's when I realized how bare-bo= nes > the current RISC-V machine_restart() actually is.. > FYI, the discussion with Aurelien started here [1]. Link: https://lore.kernel.org/all/DGZM6WUAVPPS.20Y0NIZYI4572@linux.spacemit= .com/ [1] - Troy >> >> Your approach is much better and=20 >> aligns riscv64 with other architectures, which is important as we might= =20 >> have shared PMIC drivers. >> >> Therefore: >> >> Tested-by: Aurelien Jarno >> Reviewed-by: Aurelien Jarno > Thanks. :) > > - Troy >> >> Regards >> Aurelien