From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-179.mta0.migadu.com (out-179.mta0.migadu.com [91.218.175.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28166337105 for ; Mon, 16 Mar 2026 16:22:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.179 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773678133; cv=none; b=tgFhybsJzGcqMenezO42JSzA1EzjEirTq6aL5fnefJb1kjVuxByI1z2JbDYeY3kh5DQtILS3HmMcxUcIH/hhiGGPcPoq71eVPwCh0AeJV+YXsBg3X7sgD+tOLPBnhXqhgRVY+FVk7zyYxy2jQKfvFTjs9eTHi2iPVeh0Gx3i8vg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773678133; c=relaxed/simple; bh=wnbOMj973iNMjwfJCcvrVePmzPte5is4p5QIAy19lCE=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:From:To:Cc: References:In-Reply-To; b=QZPckU5RfhdKTfuyWLPU6Dk82k9fWmd9+3xH9QGPLfGz1NOHVNhKtYfg63WyPKLlOEzGFN4OLudq/uvpApc8406x4/C7X4f0g+JOALP4ZJhhajSm4qc1ouvRAh+zy38z0w5mT3HEvmYIS8NgId3P5O2EMe50oecXDVaoD2j8is4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com; spf=pass smtp.mailfrom=cknow-tech.com; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b=G1CHmcKb; arc=none smtp.client-ip=91.218.175.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b="G1CHmcKb" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cknow-tech.com; s=key1; t=1773678128; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sKiVBNoA5DEu7rqy18+2ZGT3Fg9uiPh7qLdQNWRH0EY=; b=G1CHmcKbFX5mwfpFjdibARdCz8T1tfgVZCAJgRPK8uxCx5g8EmpSMyA3J1ZTg5s4BoBcin ToynlxXlMxee8q7yw6iQsBhbucNcQyXnlP3hTiyAqYLsv5Cfsj2+a6fdaQvzMTuE6DY3wM CVy4ZRAE7v2uTo8rHvZf/98ai/dhfJ8R18VM9vRchKjEDNT6i7JhZxlP6AggU0+LX5YIKi S2hnC05U37pqE+45ot88biPiXWVku3sujcSj2Mxt+FIoP3FUHt+OfeLQ8s22wJqlPVjXBV kY3cALfz34v+iGuEV5ORqMc5a6wy3v13PZgA53fCpqBH6ZzNEHqNy1Hdabo4OA== Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 16 Mar 2026 17:22:05 +0100 Message-Id: Subject: Re: [PATCH v2 2/3] arm64: dts: rockchip: Enable OTP controller for RK356x X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: "Diederik de Haas" To: "Heiko Stuebner" Cc: , , , , , , References: <20260312213019.13965-1-heiko@sntech.de> <20260312213019.13965-3-heiko@sntech.de> In-Reply-To: X-Migadu-Flow: FLOW_OUT Hi Heiko, On Thu Mar 12, 2026 at 10:30 PM CET, Heiko Stuebner wrote: > Enable the One Time Programmable Controller (OTPC) in RK356x and add > an initial nvmem fixed layout. I build a kernel with the nvmem patches and your patches from this series and tried it out on my NanoPi R5S with a RK3568 SoC. Navigating to ``/sys/bus/nvmem/devices/rockchip-otp0/cells`` and then doing ``hexdump `` showed all kind of values. Then I did the same with my PineNote with a RK3566 SoC and that gave different values, except for npu-leakage, which I guess is fine? So feel free to include my Tested-by: Diederik de Haas # NanoPi R5S, PineNo= te Cheers, Diederik > Signed-off-by: Heiko Stuebner > --- > arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/b= oot/dts/rockchip/rk356x-base.dtsi > index 68b48606f601..c8321af7de7d 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi > @@ -1123,6 +1123,52 @@ rng: rng@fe388000 { > status =3D "disabled"; > }; > =20 > + otp: efuse@fe38c000 { > + compatible =3D "rockchip,rk3568-otp"; > + reg =3D <0x0 0xfe38c000 0x0 0x4000>; > + clocks =3D <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>, > + <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>; > + clock-names =3D "otp", "apb_pclk", "phy", "sbpi"; > + resets =3D <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>, > + <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>; > + reset-names =3D "otp", "apb", "phy", "sbpi"; > + > + nvmem-layout { > + compatible =3D "fixed-layout"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + > + cpu_code: cpu-code@2 { > + reg =3D <0x02 0x2>; > + }; > + > + otp_cpu_version: cpu-version@8 { > + reg =3D <0x08 0x1>; > + bits =3D <3 3>; > + }; > + > + otp_id: id@a { > + reg =3D <0x0a 0x10>; > + }; > + > + cpu_leakage: cpu-leakage@1a { > + reg =3D <0x1a 0x1>; > + }; > + > + log_leakage: log-leakage@1b { > + reg =3D <0x1b 0x1>; > + }; > + > + npu_leakage: npu-leakage@1c { > + reg =3D <0x1c 0x1>; > + }; > + > + gpu_leakage: gpu-leakage@1d { > + reg =3D <0x1d 0x1>; > + }; > + }; > + }; > + > i2s0_8ch: i2s@fe400000 { > compatible =3D "rockchip,rk3568-i2s-tdm"; > reg =3D <0x0 0xfe400000 0x0 0x1000>;