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charset=UTF-8 Date: Thu, 19 Mar 2026 23:24:18 +0900 Message-Id: Cc: "Danilo Krummrich" , "Alice Ryhl" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Miguel Ojeda" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Trevor Gross" , "John Hubbard" , "Alistair Popple" , "Joel Fernandes" , "Timur Tabi" , "Zhi Wang" , , , , , Subject: Re: [PATCH 5/8] gpu: nova-core: convert FUSE registers to kernel register macro From: "Alexandre Courbot" To: "Eliot Courtney" References: <20260318-b4-nova-register-v1-0-22a358aa4c63@nvidia.com> <20260318-b4-nova-register-v1-5-22a358aa4c63@nvidia.com> In-Reply-To: X-ClientProxiedBy: TYCP286CA0202.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:385::10) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|SA3PR12MB9198:EE_ X-MS-Office365-Filtering-Correlation-Id: 53034919-98e6-4d05-d538-08de85c3370d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|1800799024|366016|376014|7416014|56012099003|22082099003|18002099003; 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>> @@ -60,16 +64,20 @@ fn signature_reg_fuse_version_ga102( >> =20 >> // `ucode_idx` is guaranteed to be in the range [0..15], making the= `read` calls provable valid >> // at build-time. >> - let reg_fuse_version =3D if engine_id_mask & 0x0001 !=3D 0 { >> - regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::read(bar, ucode_idx)= .data() >> + let reg_fuse_version: u16 =3D if engine_id_mask & 0x0001 !=3D 0 { >> + bar.read(regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_id= x)) >> + .data() >> } else if engine_id_mask & 0x0004 !=3D 0 { >> - regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::read(bar, ucode_idx= ).data() >> + bar.read(regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_i= dx)) >> + .data() >> } else if engine_id_mask & 0x0400 !=3D 0 { >> - regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::read(bar, ucode_idx).= data() >> + bar.read(regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx= )) >> + .data() >> } else { >> dev_err!(dev, "unexpected engine_id_mask {:#x}\n", engine_id_ma= sk); >> return Err(EINVAL); >> - }; >> + } >> + .into(); >> =20 >> // TODO[NUMM]: replace with `last_set_bit` once it lands. >> Ok(u16::BITS - reg_fuse_version.leading_zeros()) >> diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-co= re/fb/hal/ga100.rs >> index 629588c75778..1c03783cddef 100644 >> --- a/drivers/gpu/nova-core/fb/hal/ga100.rs >> +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs >> @@ -40,7 +40,8 @@ pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0= , addr: u64) { >> } >> =20 >> pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool { >> - !regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disable= d() >> + !bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY) >> + .display_disabled() >> } >> =20 >> /// Shift applied to the sysmem address before it is written into >> diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-co= re/fb/hal/tu102.rs >> index 515d50872224..281bb796e198 100644 >> --- a/drivers/gpu/nova-core/fb/hal/tu102.rs >> +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs >> @@ -29,7 +29,8 @@ pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0= , addr: u64) -> Result { >> } >> =20 >> pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool { >> - !regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disable= d() >> + !bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY) >> + .display_disabled() >> } >> =20 >> pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 { >> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.= rs >> index 4439464aae4d..9682a94b8b77 100644 >> --- a/drivers/gpu/nova-core/regs.rs >> +++ b/drivers/gpu/nova-core/regs.rs >> @@ -294,17 +294,19 @@ pub(crate) fn vga_workspace_addr(self) -> Option { >> =20 >> pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize =3D 16; >> =20 >> -register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100[NV_FUSE_OPT= _FPF_SIZE] { >> - 15:0 data as u16; >> -}); >> +nv_reg! { >> + NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x0082= 4100 { >> + 15:0 data; >> + } >> =20 >> -register!(NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION @ 0x00824140[NV_FUSE_OPT_= FPF_SIZE] { >> - 15:0 data as u16; >> -}); >> + NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x00824= 140 { >> + 15:0 data; >> + } >> =20 >> -register!(NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION @ 0x008241c0[NV_FUSE_OPT_F= PF_SIZE] { >> - 15:0 data as u16; >> -}); >> + NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x008241= c0 { >> + 15:0 data; >> + } >> +} > > What about using data =3D> u16 here (like below with =3D> bool), then we = can > avoid the into()?. Of course - I overlooked that, thanks for pointing it out.