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> - > - let bios =3D Vbios::new(dev, bar)?; > + let uses_sec2 =3D matches!( > + chipset.arch(), > + Architecture::Turing | Architecture::Ampere | Architecture::= Ada > + ); > =20 > let gsp_fw =3D KBox::pin_init(GspFirmware::new(dev, chipset, FIR= MWARE_VERSION), GFP_KERNEL)?; > =20 > let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; > dev_dbg!(dev, "{:#x?}\n", fb_layout); > =20 > - Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb_l= ayout)?; > - > let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::n= ew(&gsp_fw, &fb_layout))?; > =20 > - self.cmdq > - .send_command_no_wait(bar, commands::SetSystemInfo::new(pdev= , chipset))?; > - self.cmdq > - .send_command_no_wait(bar, commands::SetRegistry::new())?; > + // Architecture-specific boot path > + if uses_sec2 { > + // SEC2 path: send commands before GSP reset/boot (original = order). > + self.cmdq > + .send_command_no_wait(bar, commands::SetSystemInfo::new(= pdev, chipset))?; > + self.cmdq > + .send_command_no_wait(bar, commands::SetRegistry::new())= ?; > =20 > - gsp_falcon.reset(bar)?; > - let libos_handle =3D self.libos.dma_handle(); > - let (mbox0, mbox1) =3D gsp_falcon.boot( > - bar, > - Some(libos_handle as u32), > - Some((libos_handle >> 32) as u32), > - )?; > - dev_dbg!(pdev, "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1)= ; > - > - dev_dbg!( > - pdev, > - "Using SEC2 to load and run the booter_load firmware...\n" > - ); > - > - Self::run_booter(dev, bar, chipset, sec2_falcon, &wpr_meta)?; > + Self::boot_via_sec2( > + dev, > + bar, > + chipset, > + gsp_falcon, > + sec2_falcon, > + &fb_layout, > + &self.libos, > + &wpr_meta, > + )?; > + } else { > + Self::boot_via_fsp(dev, bar, chipset, gsp_falcon, &wpr_meta,= &self.libos)?; > + } > =20 > + // Common post-boot initialization > gsp_falcon.write_os_version(bar, gsp_fw.bootloader.app_version); > =20 > // Poll for RISC-V to become active before running sequencer > @@ -209,18 +267,27 @@ pub(crate) fn boot( > Delta::from_secs(5), > )?; > =20 > - dev_dbg!(pdev, "RISC-V active? {}\n", gsp_falcon.is_riscv_active= (bar),); > + dev_dbg!(dev, "RISC-V active? {}\n", gsp_falcon.is_riscv_active(= bar)); > =20 > - // Create and run the GSP sequencer. > - let seq_params =3D GspSequencerParams { > - bootloader_app_version: gsp_fw.bootloader.app_version, > - libos_dma_handle: libos_handle, > - gsp_falcon, > - sec2_falcon, > - dev: pdev.as_ref().into(), > - bar, > - }; > - GspSequencer::run(&self.cmdq, seq_params)?; > + // For FSP path, send commands after GSP becomes active. > + if !uses_sec2 { > + self.cmdq > + .send_command_no_wait(bar, commands::SetSystemInfo::new(= pdev, chipset))?; > + self.cmdq > + .send_command_no_wait(bar, commands::SetRegistry::new())= ?; Do you know why we need to queue these commands at a different time for the SEC2 and FSP boot methods? I don't see any reason why we couldn't pre-queue them as we do for SEC2 here, and doing that would simplify the flow considerably.