From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4AB238F95E for ; Mon, 20 Apr 2026 10:44:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776681897; cv=none; b=f2tCqmgCIERE2rd2xA5v3Cj8MGl/OxVNfYDvMufBYP3sDwIdB/Qu2DeYjpzjdujt8FQ8k7eqzjoaUfZUlMccK45yk1HrXtNaTfZw4xbs4z/SG412OPVkGKmUmeh5XSfvPh66cSijmKEzxyvvlTMoy4cIxzAiryCvoMqJIpqh7IY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776681897; c=relaxed/simple; bh=TMJkCzOessYLb1VcTlPJbCPICj+wBOUKL06CBrs8khA=; h=Mime-Version:Content-Type:Date:Message-Id:Cc:From:To:Subject: References:In-Reply-To; b=f1p4KW8pmPz0PGK3ZouktuGuHecr4nZwD4LiQd/UF9VTZfBYHAQTWIqWwjAZu4K1M//hYC8b2pDH36J1HLT1VTTII0TAkP5LdOmirfeGiLCwAnbc3fX4pDsbhHOmtKeZfIRvfBCqcBKfLW0EGuzJ5OIh7AbI3f0+xx7yUFjSx+Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tMdX5Cwi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tMdX5Cwi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3F3EFC19425; Mon, 20 Apr 2026 10:44:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776681896; bh=TMJkCzOessYLb1VcTlPJbCPICj+wBOUKL06CBrs8khA=; h=Date:Cc:From:To:Subject:References:In-Reply-To:From; b=tMdX5CwiHoXzX8CUsVQ/OzXjx8I7xpNwOcJBlDObbQv3H4ZFVp+s6ZGOIuMxZFu1l 87FXhgEmowV85SSAQ+COeSBAAGHzPWX8DhZ2mTvTI61aPRlYcXslBFJrld5alQnS1r 1TRgpRbY25k6MZpHdoASSnu9vuHSz1DdlnGBdTP0VmxnCDfp16M/VaYDFoqornyyDL 9pxOdpEPON6Au0xAiU2Dy1CTI0cmR0vf9LgNRDNl7wJv0vGDwRk6thCjlpJtnyGgLt zv1dMpbiysbd+snOZuOksjzl4+IGb+vrQaj+Z1Xyd6a+6VbxamNqNfzViIWJlaD1Sv 575Acx3/pdD5Q== Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Type: multipart/signed; boundary=73dfe8a03485c5b565fa61a9fcc3cdf1d267ae70f3a48ecb534463a67e83; micalg=pgp-sha384; protocol="application/pgp-signature" Date: Mon, 20 Apr 2026 12:44:52 +0200 Message-Id: Cc: , , , From: "Michael Walle" To: , Subject: Re: [PATCH] [v3] mtd: spi-nor: gigadevice: Add support for GD25LQ255E X-Mailer: aerc 0.20.0 References: <20260418084253.792395-1-wuweimin@huaqin.corp-partner.google.com> <792c09f5ae754bf899693f110ef1dbe0@infineon.com> In-Reply-To: <792c09f5ae754bf899693f110ef1dbe0@infineon.com> --73dfe8a03485c5b565fa61a9fcc3cdf1d267ae70f3a48ecb534463a67e83 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 On Mon Apr 20, 2026 at 11:51 AM CEST, Takahiro.Kuwano wrote: > Hi, > >>=20 >> On Sat Apr 18, 2026 at 10:42 AM CEST, Weimin Wu wrote: >> > Add support for the GigaDevice GD25LQ255E (JEDEC ID c8 60 19), >> > a 256Mbit (32MB) SPI NOR flash chip which supports SFDP. >> > >> > The chip supports 4K sector erase, dual read, and quad read modes. >> > >> > Link: https://download.gigadevice.com/Datasheet/DS-00562-GD25LQ255E-Re= v1.2.pdf >>=20 >> Please move the Link: tag above your SoB line. >>=20 >> .. >>=20 >> > diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gi= gadevice.c >> > index ef1edd0ad..22a430798 100644 >> > --- a/drivers/mtd/spi-nor/gigadevice.c >> > +++ b/drivers/mtd/spi-nor/gigadevice.c >> > @@ -82,6 +82,10 @@ static const struct flash_info gigadevice_nor_parts= [] =3D { >> > .size =3D SZ_16M, >> > .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, >> > .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, >> > + }, { >> > + /* gd25lb256 */ >> > + .id =3D SNOR_ID(0xc8, 0x60, 0x19), >> > + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP | SPI_NOR_HAS_TB | SP= I_NOR_TB_SR_BIT6, >>=20 >> Reviewed-by: Michael Walle >>=20 > The datasheet explains (in Table 5) that BP2-BP0 control the length > of protection area (all, 1/2 ... 1/64, 0) and BP3 controls upper/lower. > It looks 3 BP and 1 TB so SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB should work. > BP4 protects top or bottom 4KB to 32KB and current SWP doesn't support > that protection mechanism, right? Sorry if I missed something... Ha, you are right, thanks for pointing that out. I actually fell for the wrong comment and looked at that datasheet in the end.. for which the flags are correct. And what weird name is that gd25lq255.. Anyway. The ID matches the linked datasheet. So something is wrong here. Weimin, please test the locking properly and update the comment as Tudor already pointed out. Thanks, -michael --73dfe8a03485c5b565fa61a9fcc3cdf1d267ae70f3a48ecb534463a67e83 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iKgEABMJADAWIQTIVZIcOo5wfU/AngkSJzzuPgIf+AUCaeYDpBIcbXdhbGxlQGtl cm5lbC5vcmcACgkQEic87j4CH/hmXgF+J5yrTL1g+ijLWNJIwfr4xp8z3Nb/rM6v KIiJRwmWkPuvKlGpTOFENqDxWCVi0mDNAXwPVJ4WBSMPSbLj9CVoqC6eG6eWJfBK Nnv5LArxqw8GGxF5zqFfUOhcKEfXaVVEFzs= =8ycM -----END PGP SIGNATURE----- --73dfe8a03485c5b565fa61a9fcc3cdf1d267ae70f3a48ecb534463a67e83--