[PATCH v10 19/28] gpu: nova-core: Hopper/Blackwell: add FSP falcon EMEM operations

John Hubbard
2026-04-11T02:50:29Z

Add external memory (EMEM) read/write operations to the GPU's FSP falcon
engine. These operations use Falcon PIO (Programmed I/O) to communicate
with the FSP through indirect memory access.

Signed-off-by: John Hubbard <jhubbard@nvidia.com>
---
drivers/gpu/nova-core/falcon/fsp.rs | 149 +++++++++++++++++++++++++++-
drivers/gpu/nova-core/regs.rs | 16 +++
2 files changed, 160 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs
index 57817a594631..27344da6680c 100644
--- a/drivers/gpu/nova-core/falcon/fsp.rs
+++ b/drivers/gpu/nova-core/falcon/fsp.rs
@@ -5,12 +5,29 @@
//! The FSP falcon handles secure boot and Chain of Trust operations
//! on Hopper and Blackwell architectures, replacing SEC2's role.

-use kernel::io::register::RegisterBase;
+use kernel::{
+ io::{
+ register::{
+ RegisterBase,
+ WithBase, //
+ },
+ Io,
+ IoCapable, //
+ },
+ num::Bounded,
+ prelude::*,
+ ptr::Alignment, //
+};

-use crate::falcon::{
- FalconEngine,
- PFalcon2Base,
- PFalconBase, //
+use crate::{
+ driver::Bar0,
+ falcon::{
+ Falcon,
+ FalconEngine,
+ PFalcon2Base,
+ PFalconBase, //
+ },
+ regs,
};

/// Type specifying the `Fsp` falcon engine. Cannot be instantiated.
@@ -25,3 +42,125 @@ impl RegisterBase<PFalcon2Base> for Fsp {
}

impl FalconEngine for Fsp {}
+
+/// Maximum addressable EMEM size, derived from the 24-bit offset field
+/// in NV_PFALCON_FALCON_EMEM_CTL.
+const EMEM_MAX_SIZE: Alignment = Alignment::new::<{ 1 << 24 }>();
+
+/// I/O backend for the FSP falcon's external memory (EMEM).
+///
+/// Each 32-bit access programs a byte offset via the EMEM_CTL register,
+/// then reads or writes through the EMEM_DATA register.
+struct Emem<'a> {
+ bar: &'a Bar0,
+}
+
+impl<'a> Emem<'a> {
+ fn new(bar: &'a Bar0) -> Self {
+ Self { bar }
+ }
+}
+
+impl IoCapable<u32> for Emem<'_> {
+ unsafe fn io_read(&self, address: usize) -> u32 {
+ // PANIC: Per the `io_read` SAFETY comment, `address` is within the I/O bounds of `Self` and
+ // thus less than `EMEM_MAX_SIZE`, meaning the `else` block is never taken.
+ let Some(offset) =
+ Bounded::<usize, { EMEM_MAX_SIZE.log2() }>::try_new(address).map(Bounded::cast::<u32>)
+ else {
+ unreachable!()
+ };
+
+ self.bar.write(
+ WithBase::of::<Fsp>(),
+ regs::NV_PFALCON_FALCON_EMEM_CTL::zeroed()
+ .with_rd_mode(true)
+ .with_offset(offset),
+ );
+
+ self.bar
+ .read(regs::NV_PFALCON_FALCON_EMEM_DATA::of::<Fsp>())
+ .data()
+ }
+
+ unsafe fn io_write(&self, value: u32, address: usize) {
+ // PANIC: Per the `io_write` SAFETY comment, `address` is within the I/O bounds of `Self` and
+ // thus less than `EMEM_MAX_SIZE`, meaning the `else` block is never taken.
+ let Some(offset) =
+ Bounded::<usize, { EMEM_MAX_SIZE.log2() }>::try_new(address).map(Bounded::cast::<u32>)
+ else {
+ unreachable!()
+ };
+
+ self.bar.write(
+ WithBase::of::<Fsp>(),
+ regs::NV_PFALCON_FALCON_EMEM_CTL::zeroed()
+ .with_wr_mode(true)
+ .with_offset(offset),
+ );
+
+ self.bar.write(
+ WithBase::of::<Fsp>(),
+ regs::NV_PFALCON_FALCON_EMEM_DATA::zeroed().with_data(value),
+ );
+ }
+}
+
+impl Io for Emem<'_> {
+ fn addr(&self) -> usize {
+ 0
+ }
+
+ fn maxsize(&self) -> usize {
+ EMEM_MAX_SIZE.as_usize()
+ }
+}
+
+impl Falcon<Fsp> {
+ /// Returns an EMEM I/O accessor for this FSP falcon.
+ fn emem<'a>(&self, bar: &'a Bar0) -> Emem<'a> {
+ Emem::new(bar)
+ }
+
+ /// Writes `data` to FSP external memory at byte `offset`.
+ ///
+ /// Data is interpreted as little-endian 32-bit words.
+ /// Returns `EINVAL` if offset or data length is not 4-byte aligned.
+ #[expect(dead_code)]
+ fn write_emem(&self, bar: &Bar0, offset: u32, data: &[u8]) -> Result {
+ if offset % 4 != 0 || data.len() % 4 != 0 {
+ return Err(EINVAL);
+ }
+
+ let emem = self.emem(bar);
+ let mut off = offset as usize;
+ for chunk in data.chunks_exact(4) {
+ let word = u32::from_le_bytes([chunk[0], chunk[1], chunk[2], chunk[3]]);
+ emem.try_write32(word, off)?;
+ off += 4;
+ }
+
+ Ok(())
+ }
+
+ /// Reads FSP external memory at byte `offset` into `data`.
+ ///
+ /// Data is stored as little-endian 32-bit words.
+ /// Returns `EINVAL` if offset or data length is not 4-byte aligned.
+ #[expect(dead_code)]
+ fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut [u8]) -> Result {
+ if offset % 4 != 0 || data.len() % 4 != 0 {
+ return Err(EINVAL);
+ }
+
+ let emem = self.emem(bar);
+ let mut off = offset as usize;
+ for chunk in data.chunks_exact_mut(4) {
+ let word = emem.try_read32(off)?;
+ chunk.copy_from_slice(&word.to_le_bytes());
+ off += 4;
+ }
+
+ Ok(())
+ }
+}
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index e4de7bfffde1..5ba6c2aedd7e 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -425,6 +425,22 @@ pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
pub(crate) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 {
7:7 allow_phys_no_ctx => bool;
}
+
+ // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell).
+ // These provide the falcon external memory communication interface.
+ pub(crate) NV_PFALCON_FALCON_EMEM_CTL(u32) @ PFalconBase + 0x00000ac0 {
+ /// EMEM byte offset (must be 4-byte aligned)
+ 23:0 offset;
+ /// Write mode
+ 24:24 wr_mode => bool;
+ /// Read mode
+ 25:25 rd_mode => bool;
+ }
+
+ pub(crate) NV_PFALCON_FALCON_EMEM_DATA(u32) @ PFalconBase + 0x00000ac4 {
+ /// EMEM data register
+ 31:0 data => u32;
+ }
}

impl NV_PFALCON_FALCON_DMACTL {
--
2.53.0