From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC5D61DF751 for ; Thu, 28 May 2026 06:36:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779950194; cv=none; b=c6s9DbC9rlBwJOcf6CIxUmnA2wNLD/2ZdfZR7F0WI2Esvt9C6f3YOE7bhrCxd0vb6mgANH8BKEAwbm71rkt8Sytz7p5Db6RZMkFPoqFGP6LJdjWQwRHBqjf3DfFpFveA0IXa3s4mn2HCL3buoP2VV9XKqp7SFDStdjYlz52os2U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779950194; c=relaxed/simple; bh=jwz4chUaclB1oy+HZK62dkdOfKLQHQvg+0A7XTI2fpA=; h=Mime-Version:Content-Type:Date:Message-Id:From:To:Subject:Cc: References:In-Reply-To; b=S8MIymXjOrA7W2D5PNWPXc8GkWiGCpGhtce1WXqJkENQiX8CYOzdiz8J5jO7wisN9L54r/ziRDPguItSWhcmHIL/ui8d0ZDnE+QeeSWXFJpevJOJ9beu75otNQEE1/eaZLOspS72fojHVViJIrrbO/qXKmJCs6aqZRYXKW300Qk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l82MJ2Gl; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l82MJ2Gl" Received: by smtp.kernel.org (Postfix) with UTF8SMTPSA id 0969C1F000E9; Thu, 28 May 2026 06:36:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779950192; bh=dheGGxgFA7HJYyjPJaeFe2U1ZhHbqmehz/qjJHcKIJI=; h=Date:From:To:Subject:Cc:References:In-Reply-To; b=l82MJ2GlxPn6ij/qiCsDvt5xgkWAoLjZl/Nc6NzV4WL1WXZbMhXvfmnEEMTY2UAL8 ckJDFo3FpRYLzaX2vl28GoqU8/WwQSLzd+nmIioJJdqyS8lUjBixOQdlJSKx6irH2J /NlNVR8WOF8BDrqAw7+sshvJm+bgoLxi8hf94p3BdpcSGI6lrQiutlqJdz4ElDdfOX Q+dY7ix5K9kHtKHeUlrZb0yX7YrTIrO9LzyfAHQ0copb/jiVPb6pPt8y3LY/6Q7E6Z h1tf0WdhpOlVbwGkxTWTJ/T0RgEfYJj8oDtgo0G42wOpC+dQmv30e27WoZUQxAxs5J rgVu38Iq63Duw== Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Type: multipart/signed; boundary=246448d431d63ca955350059c67164a7fa372864f8fd507b34187c7d232c; micalg=pgp-sha384; protocol="application/pgp-signature" Date: Thu, 28 May 2026 08:36:28 +0200 Message-Id: From: "Michael Walle" To: "Cheng Ming Lin" , "Pratyush Yadav" , "Takahiro Kuwano" , "Miquel Raynal" , "Richard Weinberger" , "Vignesh Raghavendra" Subject: Re: [PATCH] mtd: spi-nor: Add support for MX25L12833F and MX25L12845G Cc: , , , "Cheng Ming Lin" X-Mailer: aerc 0.20.0 References: <20260528051751.1648246-1-linchengming884@gmail.com> In-Reply-To: <20260528051751.1648246-1-linchengming884@gmail.com> --246448d431d63ca955350059c67164a7fa372864f8fd507b34187c7d232c Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Hi, On Thu May 28, 2026 at 7:17 AM CEST, Cheng Ming Lin wrote: > From: Cheng Ming Lin > > Add support for Macronix MX25L12833F and MX25L12845G. > > The SFDP tables for these flashes only declare 1-4-4 Page Program > support in 4-byte address mode. However, since these parts operate > in 3-byte address mode, the standard SFDP parsing does not automatically > enable this capability. To address this, this patch introduces > macronix_4pp3b_late_init_fixups() to explicitly enable the 1-4-4 > Page Program. > > Signed-off-by: Cheng Ming Lin ... > --- a/drivers/mtd/spi-nor/macronix.c > +++ b/drivers/mtd/spi-nor/macronix.c > @@ -83,6 +83,18 @@ mx25l3255e_late_init_fixups(struct spi_nor *nor) > return 0; > } > =20 > +static int > +macronix_4pp3b_late_init_fixups(struct spi_nor *nor) > +{ > + struct spi_nor_flash_parameter *params =3D nor->params; > + > + params->hwcaps.mask |=3D SNOR_HWCAPS_PP_1_4_4; > + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_4_4], > + SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4); > + > + return 0; > +} > + > static const struct spi_nor_fixups mx25l25635_fixups =3D { > .post_bfpt =3D mx25l25635_post_bfpt_fixups, > .post_sfdp =3D macronix_qpp4b_post_sfdp_fixups, > @@ -96,6 +108,10 @@ static const struct spi_nor_fixups mx25l3255e_fixups = =3D { > .late_init =3D mx25l3255e_late_init_fixups, > }; > =20 > +static const struct spi_nor_fixups macronix_4pp3b_fixups =3D { > + .late_init =3D macronix_4pp3b_late_init_fixups, > +}; > + > static const struct flash_info macronix_nor_parts[] =3D { > { > .id =3D SNOR_ID(0xc2, 0x20, 0x10), > @@ -130,9 +146,10 @@ static const struct flash_info macronix_nor_parts[] = =3D { > .size =3D SZ_8M, > .no_sfdp_flags =3D SECT_4K, > }, { > - /* MX25L12805D */ > + /* MX25L12805D, MX25L12833F, MX25L12845G */ > .id =3D SNOR_ID(0xc2, 0x20, 0x18), > .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP, > + .fixups =3D ¯onix_4pp3b_fixups, It looks like you're getting bitten by the ID reuse. You can't just unconditionally add the quad PP because as far as I can see the=20 MX25L12805D [1] is just a standard single bit i/o flash and doesn't support the 4PP. -michael [1] https://www.macronix.com/Lists/Datasheet/Attachments/8582/MX25L12805D,%= 203V,%20128Mb,%20v1.2.pdf --246448d431d63ca955350059c67164a7fa372864f8fd507b34187c7d232c Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iKgEABMJADAWIQTIVZIcOo5wfU/AngkSJzzuPgIf+AUCahfibBIcbXdhbGxlQGtl cm5lbC5vcmcACgkQEic87j4CH/gPRQGAjl03oIqsBP5vbC4PtnCKam0IIBQHq4GQ vMVo5TodbnqivTPnXDgRzWDQJn+0pBpmAYC8dsCBNc8abFTVyDkc5RoGwkyO5z8e BH0ozpysvX2GuuKdrrul98JOzYeTaJlT2KQ= =GBr5 -----END PGP SIGNATURE----- --246448d431d63ca955350059c67164a7fa372864f8fd507b34187c7d232c--