From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 666A21D5CD1 for ; Mon, 8 Jun 2026 01:21:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780881693; cv=none; b=BQZbdHK0kZqSxnH8ljX+FZ34+I6t5zzZs3s25x3qRhm1jrXBVSi7uRtxP6WjbRU9geBpoBj9GioEe6uzl05PwQFT5MnE5dTRMI/zPEasIE0vgEeJ8mvpJ+QiaDbw4PuMP1vFPwBUxJdDTM1+LxM0mPUKzVB6+0d5DYAnzFkFCis= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780881693; c=relaxed/simple; bh=195QwlmraNwRwXBAofrP5QnBTZsirmlXkk9AtKSVyrE=; h=Mime-Version:Content-Type:Date:Message-Id:Cc:Subject:From:To: References:In-Reply-To; b=okriysai3wXWtABKt1mHgQJ2k3K35k9b3ynXdnN7I7pUvIDGUPHxFTyEs5vJ/+W97j9SqQaxRQKZey3GwqwCkRuhIq/uvJ1sogN0jJsGdW2U/cSQ72hZZ3iT/dMvpgBVjvkheQoh0xuhgucmVX3nxUP9nCZUktPrY+KB1ggL3Ko= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=cG082HsA; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="cG082HsA" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1780881680; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IxEvUfH9QoMBWe5UKI9XOfbgGKkqlVzL0+nWkvvLnp0=; b=cG082HsAL/LltPk8sH5lS49pkSdIyH/gCKie6DiDgLYw5M+G1NAIviv4LSBHrFS+4WYdBK GThT9HEjxG9irElzwkn/MnlxqyDKA2QzyH05mAzPGYmifYY6+2CabcDCj+NvV5ODOCPJL8 JPbdKe/Z6FcDKpqB3nyb8Ovjxg2CrhU= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 08 Jun 2026 09:21:01 +0800 Message-Id: Cc: , , , "Aurelien Jarno" Subject: Re: [PATCH v3] riscv: disable local interrupts and stop other CPUs before reboot/shutdown X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: "Troy Mitchell" To: "Troy Mitchell" , "Troy Mitchell" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" References: <20260330-v7-0-rc1-rv-dis-int-before-restart-v3-1-5a0577fcd136@linux.spacemit.com> In-Reply-To: X-Migadu-Flow: FLOW_OUT On Wed Apr 29, 2026 at 7:44 PM CST, Troy Mitchell wrote: > Hi all, > > On Mon Mar 30, 2026 at 5:58 PM CST, Troy Mitchell wrote: >> From: Troy Mitchell >> >> Currently, the RISC-V implementation of machine_restart(), machine_halt(= ), >> and machine_power_off() invokes the kernel teardown chains (e.g., >> do_kernel_restart()) with local interrupts enabled and other CPUs still >> running. >> >> This implementation fails to provide a deterministic execution environme= nt >> for registered handlers in the restart or power-off notifier chains. The= se >> chains are intended to be executed in a strict atomic and single-threade= d >> context. >> >> Specifically, under CONFIG_PREEMPT_RCU, rcu_read_lock() does not increme= nt >> the preempt_count. If local interrupts remain enabled, the environment >> is not guaranteed to be atomic. This can lead to a context misidentifica= tion >> within generic kernel teardown code, causing it to incorrectly enter >> non-atomic paths (such as attempting to acquire sleeping locks), which >> results in fatal "scheduling while atomic" splats or system hangs. >> >> Additionally, stopping other CPUs ensures the primary CPU has exclusive >> access to the hardware state during the final teardown phase, preventing >> unpredictable interference from other active cores. >> >> Align RISC-V with other major architectures by disabling local interrupt= s >> and stopping other CPUs at the beginning of the shutdown sequences. This >> guarantees the architectural expectations of the kernel's restart and >> power-off handlers are met. >> >> Signed-off-by: Troy Mitchell >> Tested-by: Aurelien Jarno > Gentle ping on this patch. Is there anything I should change or any > concerns with the approach? Just a gentle ping on this series.=20 Please let me know if anyone has any feedback or if there is anything=20 I should update. - Troy