From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-172.mta1.migadu.com (out-172.mta1.migadu.com [95.215.58.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B834399CEE for ; Wed, 1 Jul 2026 18:50:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782931850; cv=none; b=kasezydPNT4wgEtF8pxxrcToxyPIJtdmMj6v1t0CPAaUzgupi9Rys8mQtphH8oTc3eMUHD+Ax8iXE4gcNeKxzuj8lJD+lM9jqC0l30qM7HWqSEYp9PzJIr7FKnQdpX5NzIuI/gUdLBfsA3D0GmaWY+CGHu7GpkQGggTTiMgD8kI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782931850; c=relaxed/simple; bh=N2yODu55UjYK4SxeCqBDkWGQxeiqAO0TNeLeObpY+00=; h=Mime-Version:Content-Type:Date:Message-Id:Cc:Subject:From:To: References:In-Reply-To; b=tDzFzNoylPjegQqZD8W3VUMMUan+GCU2/0/sT2nEw9RT/uOLWQqXMMUD8m8vPlWxlfQOQ1ciQ/jqO1x/BdFDCZP7y7/Za4ObvEqV2nHZMDkM/bfrxH5weJHcCuWPO2iMedgfNgvrwc/rL7YfAEqzt50rEfvjrRQ8RPT3O5f5Meg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com; spf=pass smtp.mailfrom=cknow-tech.com; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b=I0/ovo7n; arc=none smtp.client-ip=95.215.58.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b="I0/ovo7n" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cknow-tech.com; s=key1; t=1782931843; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9u4pmteNiZYFsZdE5aO2Vb1vL6vq7YhBb/NzlG505K0=; b=I0/ovo7nLUuCM6+HSchB9d0K3LcYYcf3K8TthQG7aQpr5LnmCvFP34F/FZSgY9GxC0kYXA sGJ9ghp4p8qMP/aZdwg+SNcwTk0V4F+uo94vUO0zPQUh2bFBHEwsGol2V73RkJ6JG4EqZZ rDZ0avqpfpIQD2dhrbzgC+Zwx5DzaVeszi2tY7IsOUCCAeJdpcsJHabYI31A0VR0xy9j3+ XpCmlFLe7eSs2T2cIymWx09fJ4W7koYHxQXcbI3GMlMNJ6lly0m8hTbOJOtulfsMlcau6m CBH9s4rHl3bVRBMmtuIRwMgJ2aCroYuzyEa+FMs6hKI2UQT2fr35EgoGnAmj7Q== Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 01 Jul 2026 20:50:16 +0200 Message-Id: Cc: , , , , , =?utf-8?q?Thomas_Niederpr=C3=BCm?= , "Simon Wright" , "Sashiko" Subject: Re: [PATCH v4 0/8] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: "Diederik de Haas" To: "Cristian Ciocaltea" , "Vinod Koul" , "Neil Armstrong" , "Heiko Stuebner" , "Algea Cao" , "Dmitry Baryshkov" References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> X-Migadu-Flow: FLOW_OUT Hi Cristian, On Fri Jun 12, 2026 at 1:46 AM CEST, Cristian Ciocaltea wrote: > This series provides a set of bug fixes and cleanups for the Rockchip > Samsung HDPTX PHY driver. > > The first part of the series addresses clock rate calculation and > synchronization issues. Specifically, it fixes edge cases where the PHY > PLL is pre-programmed by an external component (like a bootloader) or > when changing the color depth (bpc) while keeping the modeline constant. > Because the Common Clock Framework .set_rate() callback might not be > invoked if the pixel clock remains unchanged, this previously led to > out-of-sync states between CCF and the actual HDMI PHY configuration. > > The second part focuses on code cleanups and modernizing the register > access. Now that dw_hdmi_qp driver has fully switched to using > phy_configure(), we can drop the deprecated TMDS rate setup workarounds > and the restrict_rate_change flag logic. Finally, it refactors the > driver to consistently use standard bitfield macros. I built a 7.2-rc1 based kernel with this patch set and used that on my NanoPC-T6 LTS connected to my 4K TV. The kernel also has the HDMI 2.0 patch set, so I can get 4K@60 with it. When I then tried to switch to 10bpc with ``modetest -M rockchip -w 86:'max bpc':10`` nothing happened. But that's expected as my TV only supports HDMI 2.0 and not HDMI 2.1. When I add ``video=3DHDMI-A-1:1920x1080@60`` to the kernel command line, th= en it starts up with 10bpc and I can change to 8bpc and back to 10bpc. So feel free to add my Tested-by: Diederik de Haas # NanoPC-T6 LTS Cheers, Diederik > > Signed-off-by: Cristian Ciocaltea > --- > Changes in v4: > - Added new patches to address new findings from Sashiko: > * Prevent divide-by-zero when computing clk rate > * Fix rate recalculation for 3.2GHz FRL > - Updated patch "Consistently use bitfield macros" to handle a few more > bit operations > - Link to v3: https://patch.msgid.link/20260611-hdptx-clk-fixes-v3-0-67b1= b0c00e16@collabora.com > > Changes in v3: > - Replaced div_u64() with DIV_ROUND_CLOSEST_ULL() in Patch 1 (Sashiko) > - Fixed theoretical usage_count unbalanced issue in Patch 2 (Sashiko) > - Rebased series onto latest phy/next > - Link to v2: https://patch.msgid.link/20260511-hdptx-clk-fixes-v2-0-664e= 41379cab@collabora.com > > Changes in v2: > - Collected Tested-by tags from Thomas and Simon > - Fixed a typo in commit description of patch 1 > - Added a comment in patch 2 explaining why PLL config errors are > ignored for rk_hdptx_phy_consumer_get() > - Added a missed FIELD_GET conversion for lcpll_hw.pms_sdiv in patch 6 > - Rebased onto latest phy/fixes > - Link to v1: https://lore.kernel.org/r/20260227-hdptx-clk-fixes-v1-0-f99= 8f2762d0f@collabora.com > > --- > Cristian Ciocaltea (8): > phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc > phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing= clk rate > phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL > phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes > phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround > phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling > phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_W= M16() > phy: rockchip: samsung-hdptx: Consistently use bitfield macros > > drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 266 +++++++++++-----= ------ > 1 file changed, 130 insertions(+), 136 deletions(-) > --- > base-commit: 293e19f416fa3f233a2fb013258f7abcb39ad6ed > change-id: 20260227-hdptx-clk-fixes-47426632f862 > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip