From: "Michael Walle" <mwalle@kernel.org>
To: "Chen Minqiang" <ptpt52@gmail.com>,
"Pratyush Yadav" <pratyush@kernel.org>,
"Miquel Raynal" <miquel.raynal@bootlin.com>,
"Richard Weinberger" <richard@nod.at>,
"Vignesh Raghavendra" <vigneshr@ti.com>
Cc: "Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] mtd: spi-nor: allow force unlocking via DT property
Date: Mon, 10 Aug 2026 08:30:11 +0200 [thread overview]
Message-ID: <DKL1W2D3OJ5J.2VW3B1VPH5LHF@kernel.org> (raw)
In-Reply-To: <20260806112418.14695-1-ptpt52@gmail.com>
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On Thu Aug 6, 2026 at 1:24 PM CEST, Chen Minqiang wrote:
> Hi,
>
> Thank you for your valuable insight!
>
> You are completely right that for unlisted/generic chips that feature a 4-bit
> BP layout (BP3 at bit 5 or bit 6) or a CMP (Complement Protect) bit in SR2,
> spi_nor_unlock() won't clear those extra bits without the corresponding flags
> (SNOR_F_HAS_4BIT_BP / SNOR_F_HAS_SR2_CMP_BIT6) set by the ID database or SFDP.
Is this AI assisted?
> However, in practice:
> 1. The vast majority of 3.3V/1.8V generic SPI NOR flashes (e.g. 4MB-16MB chips
> commonly found in vendor devices like Tenda AX12L Pro) use the standard
> 3-bit BP (BP0-BP2, SR1 bits 2..4).
> 2. The current main issue is that even for these standard 3-bit BP chips, the
> kernel currently skips spi_nor_try_unlock_all() completely at boot time if
> CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is set (for non-volatile chips)
> or if SNOR_F_HAS_LOCK is not set in chip flags. As a result, status registers
> locked by factory bootloaders are never cleared.
>
> `linux,force-sr-unlock` serves as a pragmatic DT override to force the unlock
> attempt at probe time.
>
> To address your point regarding 4-bit BP and CMP bits for unlisted chips, we
> have two potential options:
>
> Option A (Current Best-Effort):
> Keep the patch as-is, treating `linux,force-sr-unlock` as a best-effort DT
> trigger to invoke standard spi_nor_unlock(). It successfully unlocks the vast
> majority of standard 3-bit BP generic chips. For rare unlisted chips with 4-bit
> BP or CMP bits, explicit entries can still be added to the ID database when
> discovered.
>
> Option B (Aggressive Force-Clear):
> When `linux,force-sr-unlock` is present in DT, enhance spi_nor_try_unlock_all()
> to perform a broader clear operation on SR1 (masking bits 2..6 to clear BP0-BP3/TB)
> and SR2 (clearing CMP bit if SR2 is readable).
>
> Which approach would you prefer? I'd be happy to revise the patch based on your
> guidance.
This patch won't fly as is. You're missing the dt-bindings patch
(which I doubt will be accepted) and I really don't like this
approach. First, why would you unlock a flash automatically? I've
worked hard, to get rid of that anti-feature. Second, what if you
still loose the flash "lottery"?
-michael
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next prev parent reply other threads:[~2026-08-10 6:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <2026-08-05171214.2934-1-ptpt52@gmail.com>
2026-08-06 11:24 ` [PATCH] mtd: spi-nor: allow force unlocking via DT property Chen Minqiang
2026-08-10 6:30 ` Michael Walle [this message]
2026-08-06 11:37 ` [PATCH v2] " Chen Minqiang
2026-08-05 17:12 [PATCH] " Chen Minqiang
2026-08-06 5:41 ` Takahiro.Kuwano
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