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Date:   Mon, 17 Oct 2022 18:24:22 +0100
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH v2 4/4] clk: Add Ingenic JZ4755 CGU driver
To:     Siarhei Volkau <lis8215@gmail.com>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org
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        <20221016150110.3020451-5-lis8215@gmail.com>
        <0S4WJR.4KB18PR21S9K1@crapouillou.net>
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Le lun., oct. 17 2022 at 20:10:56 +0300, Siarhei Volkau=20
<lis8215@gmail.com> a =C3=A9crit :
> =D0=BF=D0=BD, 17 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 12:24, Paul Cerc=
ueil=20
> <paul@crapouillou.net>:
>=20
>>  > +     [JZ4755_CLK_AIC] =3D {
>>  > +             "aic", CGU_CLK_GATE,
>>  > +             .parents =3D { JZ4755_CLK_I2S, -1, -1, -1 },
>>=20
>>  Wrong parent here, should be JZ4755_CLK_EXT_HALF.
>=20
> I don't  agree, see Figure 20-13 in the JZ4755 PM.

20-13 describes the I2S clock, no?

AIC clock's parent is EXT/2 according to the diagram in 8.2.2.

>>  Well it would be good to know...
>=20
> Indeed, I will try to figure it out.

Cheers,
-Paul