[PATCH v2 0/2] fpga: dfl: optional VSEC for start of dfl

matthew.gerlach
2020-11-18T19:01:01Z

The start of a Device Feature List (DFL) is currently assumed to be at
Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c. This patchset
adds support for the start one or more DFLs to be specified in a
Vendor-Specific Capability (VSEC) structure in PCIe config space. If no
such VSEC structure exists, then the start is assumed to be
Bar0/Offset 0 for backward compatibility.

Matthew Gerlach (2):
fpga: dfl: refactor cci_enumerate_feature_devs()
fpga: dfl: look for vendor specific capability

Documentation/fpga/dfl.rst | 13 +++
drivers/fpga/dfl-pci.c | 163 +++++++++++++++++++++++++++++--------
2 files changed, 141 insertions(+), 35 deletions(-)

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2.25.2