From: Conor Dooley <conor@kernel.org>
To: Evan Green <evan@rivosinc.com>
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Bresticker <abrestic@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <apatel@ventanamicro.com>,
Arnd Bergmann <arnd@arndb.de>, Atish Patra <atishp@rivosinc.com>,
Bagas Sanjaya <bagasdotme@gmail.com>,
Celeste Liu <coelacanthus@outlook.com>,
Conor Dooley <conor.dooley@microchip.com>,
Dao Lu <daolu@rivosinc.com>, Guo Ren <guoren@kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Randy Dunlap <rdunlap@infradead.org>,
Ruizhe Pan <c141028@gmail.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Tobias Klauser <tklauser@distanz.ch>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 2/6] RISC-V: Add a syscall for HW probing
Date: Wed, 15 Feb 2023 21:10:23 +0000 [thread overview]
Message-ID: <Y+1KPzh9xnyKXf0W@spud> (raw)
In-Reply-To: <CALs-HssScpGxAN+TBA8PtaVHwJvmudqmXUaSZDFBiu3k4Tb3nw@mail.gmail.com>
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heh, this came in right as I went to check out by branch with this on it
and look at the rest of the series.
On Wed, Feb 15, 2023 at 12:49:35PM -0800, Evan Green wrote:
> On Tue, Feb 14, 2023 at 3:51 PM Conor Dooley <conor@kernel.org> wrote:
> > On Mon, Feb 06, 2023 at 12:14:51PM -0800, Evan Green wrote:
> > > +On success 0 is returned, on failure a negative error code is returned.
> > > +
> > > +The following keys are defined:
> > > +
> > > +* :RISCV_HWPROBE_KEY_MVENDORID:: Contains the value of :mvendorid:, as per the
> > > + ISA specifications.
> >
> > "per the ISA specifications" sounds like dangerous wording to me! ;)
>
> I can replace "per the ISA specifications" with "as defined by the
> RISC-V privileged architecture specification" to try and make that
> more crisp.
Meh was a comment about not trusting the ISA specs, not an attempt to
be a pedant!
> > > +#define RISCV_HWPROBE_KEY_MVENDORID 0
> > > +#define RISCV_HWPROBE_KEY_MARCHID 1
> > > +#define RISCV_HWPROBE_KEY_MIMPID 2
> > > +/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
> >
> > Can't wait for that to get forgotten!
>
> I know. I could add an if (pair->key > RISCV_HWPROBE_MAX_KEY) goto
> unrecognized_key, with a label at the default switch case, which would
> effectively be a runtime guard against it. I opted not to as it's
> aesthetically harsh, but anyone can holler if they want it.
The other question to ask is, do we need RISCV_HWPROBE_MAX_KEY?
What's it for?
> > > diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h
> > > index 73d7cdd2ec49..37d47302322a 100644
> > > --- a/arch/riscv/include/uapi/asm/unistd.h
> > > +++ b/arch/riscv/include/uapi/asm/unistd.h
> > > @@ -43,3 +43,11 @@
> > > #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
> > > #endif
> > > __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
> > > +
> > > +/*
> > > + * Allows userspace to probe
> >
> > That comment looks chopped off midway through.
>
> Whoops yes I
If you could flesh it
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next prev parent reply other threads:[~2023-02-15 21:11 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 20:14 [PATCH v2 0/6] RISC-V Hardware Probing User Interface Evan Green
2023-02-06 20:14 ` [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header Evan Green
2023-02-14 21:38 ` Conor Dooley
2023-02-14 21:57 ` Evan Green
2023-02-06 20:14 ` [PATCH v2 2/6] RISC-V: Add a syscall for HW probing Evan Green
2023-02-07 6:13 ` Greg KH
2023-02-07 6:32 ` Conor Dooley
2023-02-09 17:09 ` Evan Green
2023-02-09 17:13 ` Greg KH
2023-02-09 17:22 ` Jessica Clarke
2023-02-10 6:48 ` Greg KH
2023-02-09 18:41 ` Evan Green
2023-02-10 6:50 ` Greg KH
2023-02-07 23:16 ` kernel test robot
2023-02-14 23:51 ` Conor Dooley
2023-02-15 8:04 ` Andrew Jones
2023-02-15 20:49 ` Evan Green
2023-02-15 21:10 ` Conor Dooley [this message]
2023-02-15 9:56 ` Arnd Bergmann
2023-02-15 21:14 ` Evan Green
2023-02-15 22:43 ` Jessica Clarke
2023-02-16 13:28 ` Arnd Bergmann
2023-02-16 23:18 ` Evan Green
2023-02-06 20:14 ` [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Evan Green
2023-02-15 21:25 ` Conor Dooley
2023-02-15 22:09 ` Conor Dooley
2023-02-06 20:14 ` [PATCH v2 4/6] dt-bindings: Add RISC-V misaligned access performance Evan Green
2023-02-06 21:49 ` Rob Herring
2023-02-07 17:05 ` Rob Herring
2023-02-08 12:45 ` David Laight
2023-02-09 16:51 ` Palmer Dabbelt
2023-02-28 14:56 ` Rob Herring
2023-02-14 21:26 ` Conor Dooley
2023-02-15 20:50 ` Evan Green
2023-02-06 20:14 ` [PATCH v2 5/6] RISC-V: hwprobe: Support probing of " Evan Green
2023-02-07 7:02 ` kernel test robot
2023-02-15 21:57 ` Conor Dooley
2023-02-18 0:15 ` Evan Green
2023-02-06 20:14 ` [PATCH v2 6/6] selftests: Test the new RISC-V hwprobe interface Evan Green
2023-02-06 21:27 ` Mark Brown
2023-02-09 18:44 ` Evan Green
2023-02-06 21:11 ` [PATCH v2 0/6] RISC-V Hardware Probing User Interface Jessica Clarke
2023-02-06 22:47 ` Heinrich Schuchardt
2023-02-09 16:56 ` Palmer Dabbelt
2023-02-06 22:32 ` Conor Dooley
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