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From: Simon Horman <simon.horman@corigine.com>
To: "Clément Léger" <clement.leger@bootlin.com>
Cc: "Andrew Lunn" <andrew@lunn.ch>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"Vladimir Oltean" <olteanv@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Herve Codina" <herve.codina@bootlin.com>,
	"Miquèl Raynal" <miquel.raynal@bootlin.com>,
	"Milan Stevanovic" <milan.stevanovic@se.com>,
	"Jimmy Lalande" <jimmy.lalande@se.com>,
	"Pascal Eberhard" <pascal.eberhard@se.com>,
	"Arun Ramadoss" <Arun.Ramadoss@microchip.com>,
	linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] net: dsa: rzn1-a5psw: add vlan support
Date: Thu, 9 Feb 2023 11:38:04 +0100	[thread overview]
Message-ID: <Y+TNDFovmcjy+ctb@corigine.com> (raw)
In-Reply-To: <20230208160453.325783-4-clement.leger@bootlin.com>

On Wed, Feb 08, 2023 at 05:04:53PM +0100, Clément Léger wrote:
> Add support for vlan operation (add, del, filtering) on the RZN1
> driver. The a5psw switch supports up to 32 VLAN IDs with filtering,
> tagged/untagged VLANs and PVID for each ports.
> 
> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
> ---
>  drivers/net/dsa/rzn1_a5psw.c | 167 +++++++++++++++++++++++++++++++++++
>  drivers/net/dsa/rzn1_a5psw.h |   8 +-
>  2 files changed, 172 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c
> index 0ce3948952db..de6b18ec647d 100644
> --- a/drivers/net/dsa/rzn1_a5psw.c
> +++ b/drivers/net/dsa/rzn1_a5psw.c
> @@ -583,6 +583,147 @@ static int a5psw_port_fdb_dump(struct dsa_switch *ds, int port,
>  	return ret;
>  }
>  
> +static int a5psw_port_vlan_filtering(struct dsa_switch *ds, int port,
> +				     bool vlan_filtering,
> +				     struct netlink_ext_ack *extack)
> +{
> +	u32 mask = BIT(port + A5PSW_VLAN_VERI_SHIFT) |
> +		   BIT(port + A5PSW_VLAN_DISC_SHIFT);
> +	struct a5psw *a5psw = ds->priv;
> +	u32 val = 0;
> +
> +	if (vlan_filtering)
> +		val = BIT(port + A5PSW_VLAN_VERI_SHIFT) |
> +		      BIT(port + A5PSW_VLAN_DISC_SHIFT);

nit: could this be expressed as follows?

	val = vlan_filtering ? mask : 0 ?

> +
> +	a5psw_reg_rmw(a5psw, A5PSW_VLAN_VERIFY, mask, val);
> +
> +	return 0;
> +}

...

  reply	other threads:[~2023-02-09 10:39 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-08 16:04 [PATCH 0/3] net: dsa: rzn1-a5psw: add supoport for vlan and .port_bridge_flags Clément Léger
2023-02-08 16:04 ` [PATCH 1/3] net: dsa: rzn1-a5psw: use a5psw_reg_rmw() to modify flooding resolution Clément Léger
2023-02-08 16:04 ` [PATCH 2/3] net: dsa: rzn1-a5psw: add support for .port_bridge_flags Clément Léger
2023-02-08 16:04 ` [PATCH 3/3] net: dsa: rzn1-a5psw: add vlan support Clément Léger
2023-02-09 10:38   ` Simon Horman [this message]
2023-02-09 11:11     ` Clément Léger

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