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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id o2-20020a170902d4c200b0016dbdf7b97bsm1855468plg.266.2022.10.07.13.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Oct 2022 13:02:39 -0700 (PDT) Date: Fri, 7 Oct 2022 20:02:36 +0000 From: Sean Christopherson To: Like Xu Cc: Paolo Bonzini , Jim Mattson , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/3] KVM: x86/pmu: Limit the maximum number of supported Intel GP counters Message-ID: References: <20220919091008.60695-1-likexu@tencent.com> <20220919091008.60695-2-likexu@tencent.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220919091008.60695-2-likexu@tencent.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 19, 2022, Like Xu wrote: > From: Like Xu > > The Intel Architectural IA32_PMCx MSRs addresses range allows for > a maximum of 8 GP counters. A local macro (named KVM_INTEL_PMC_MAX_GENERIC) > is introduced to take back control of this virtual capability to avoid > errors introduced by the out-of-bound counter emulations. Phrase changelogs as commands. > Suggested-by: Jim Mattson > Signed-off-by: Like Xu > Reviewed-by: Jim Mattson > --- > arch/x86/include/asm/kvm_host.h | 6 +++++- > arch/x86/kvm/pmu.c | 2 +- > arch/x86/kvm/vmx/pmu_intel.c | 4 ++-- > arch/x86/kvm/x86.c | 12 +++++++----- > 4 files changed, 15 insertions(+), 9 deletions(-) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index 2c96c43c313a..17abcf5c496a 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -501,6 +501,10 @@ struct kvm_pmc { > bool intr; > }; > > +/* More counters may conflict with other existing Architectural MSRs */ > +#define KVM_INTEL_PMC_MAX_GENERIC 8 This is weird and backwards. Common x86 code shouldn't "prefer" Intel over AMD, or vice versa. Similar to KVM_MAX_NR_USER_RETURN_MSRS, the way to do this is to define KVM's common software limit, and then verify that the vendor limits are below that common limit. E.g. #define KVM_MAX_NR_PMU_GP_COUNTERS 8 and then add compile-time assertions that Intel stays below the max (and obviously AMD as well). > +#define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1) > +#define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1) These are Intel specific, correct? I.e. "arch" means "Intel architectural MSRs"? The perf-defined names are out of KVM's control, but adding what appears to be generic #defines in common KVM that are actually Intel specific is confusing. Given that there's only a single user, I think the easiest thing is to just open code the users, e.g. case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + KVM_MAX_NR_PMU_GP_COUNTERS - 1: if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= min(KVM_MAX_NR_PMU_GP_COUNTERS, kvm_pmu_cap.num_counters_gp)) continue; break; case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + KVM_MAX_NR_PMU_GP_COUNTERS - 1: if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) continue; break;