From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6387FC4332F for ; Wed, 9 Nov 2022 12:44:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230113AbiKIMoD (ORCPT ); Wed, 9 Nov 2022 07:44:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbiKIMoA (ORCPT ); Wed, 9 Nov 2022 07:44:00 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12C9121E2E for ; Wed, 9 Nov 2022 04:43:59 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C2D67B81E2D for ; Wed, 9 Nov 2022 12:43:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2C010C43470; Wed, 9 Nov 2022 12:43:55 +0000 (UTC) Date: Wed, 9 Nov 2022 12:43:51 +0000 From: Catalin Marinas To: Yunfeng Ye Cc: will@kernel.org, wangkefeng.wang@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linfeilong@huawei.com Subject: Re: [PATCH 4/5] arm64: mm: Support ASID isolation feature Message-ID: References: <20221017083203.3690346-1-yeyunfeng@huawei.com> <20221017083203.3690346-5-yeyunfeng@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221017083203.3690346-5-yeyunfeng@huawei.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 17, 2022 at 04:32:02PM +0800, Yunfeng Ye wrote: > After a rollover, the global generation will be flushed, which will > cause the process mm->context.id on all CPUs do not match the > generation. Thus, the process will compete for the global spinlock lock > to reallocate a new ASID and refresh the TLBs of all CPUs on context > switch. This will lead to the increase of scheduling delay and TLB miss. > > In some delay-sensitive scenarios, for example, part of CPUs are > isolated, only a limited number of processes are deployed to run on the > isolated CPUs. In this case, we do not want these key processes to be > affected by the rollover of ASID. Part of this commit log should also go in the cover letter and it would help to back this up by some numbers, e.g. what percentage improvement you get with this patchset by running hackbench on an isolated CPU. In theory it looks like CPU isolation would benefit from this patchset but we try not to touch this code often, so any modification should come with proper justification, backed by numbers. Note that I haven't reviewed the algorithm you are proposing in detail, only had a brief look. -- Catalin