Re: [PATCH v4 3/7] riscv: errata: Add Andes alternative ports

Lad, Prabhakar
2022-11-24T19:15:28Z

Hi Heiko,

Thank you for the review.

On Thu, Nov 24, 2022 at 6:25 PM Heiko Stübner <heiko@sntech.de> wrote:
>
> Am Donnerstag, 24. November 2022, 18:22:03 CET schrieb Prabhakar:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add required ports of the Alternative scheme for Andes CPU cores.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > RFC v3 -> v4
> > * New patch
> > ---
>
> > diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
> > index a1055965fbee..81828e80f6dc 100644
> > --- a/arch/riscv/errata/Makefile
> > +++ b/arch/riscv/errata/Makefile
> > @@ -1,2 +1,3 @@
> > obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
> > obj-$(CONFIG_ERRATA_THEAD) += thead/
> > +obj-$(CONFIG_ERRATA_ANDES) += andes/
>
> alphabetical sorting please
>
>
> > diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> > new file mode 100644
> > index 000000000000..ec3e052ca8c7
> > --- /dev/null
> > +++ b/arch/riscv/errata/andes/errata.c
> > @@ -0,0 +1,68 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Erratas to be applied for Andes CPU cores
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corporation.
> > + *
> > + * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +
> > +#include <asm/alternative.h>
> > +#include <asm/cacheflush.h>
> > +#include <asm/errata_list.h>
> > +#include <asm/patch.h>
> > +#include <asm/vendorid_list.h>
> > +
> > +static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid)
> > +{
> > + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))
> > + return false;
> > +
> > + if (arch_id != 0x8000000000008a45 || impid != 0x500)
> > + return false;
> > +
> > + riscv_cbom_block_size = 1;
>
> as this is mainly to make the core cbo code happy, maybe add a comment
> above that line to explain.
>
Agreed, I'll add a comment here.

>
> > + riscv_noncoherent_supported();
> > +
> > + return true;
> > +}
> > +
>
> > diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
> > index 6511dd73e812..d8012af30cbd 100644
> > --- a/arch/riscv/include/asm/alternative.h
> > +++ b/arch/riscv/include/asm/alternative.h
> > @@ -46,6 +46,9 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> > void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> > unsigned long archid, unsigned long impid,
> > unsigned int stage);
> > +void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> > + unsigned long archid, unsigned long impid,
> > + unsigned int stage);
>
> again alphabetical please (i.e. above sifive)
>
>
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index 4180312d2a70..2ba7e6e74540 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -9,6 +9,11 @@
> > #include <asm/csr.h>
> > #include <asm/vendorid_list.h>
> >
> > +#ifdef CONFIG_ERRATA_ANDES
> > +#define ERRATA_ANDESTECH_NO_IOCP 0
> > +#define ERRATA_ANDESTECH_NUMBER 1
> > +#endif
> > +
> > #ifdef CONFIG_ERRATA_SIFIVE
> > #define ERRATA_SIFIVE_CIP_453 0
> > #define ERRATA_SIFIVE_CIP_1200 1
> > diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
> > index a7d26a00beea..4ded3e9aa3bc 100644
> > --- a/arch/riscv/kernel/alternative.c
> > +++ b/arch/riscv/kernel/alternative.c
> > @@ -47,6 +47,11 @@ static void __init_or_module riscv_fill_cpu_mfr_info(struct cpu_manufacturer_inf
> > case THEAD_VENDOR_ID:
> > cpu_mfr_info->patch_func = thead_errata_patch_func;
> > break;
> > +#endif
> > +#ifdef CONFIG_ERRATA_ANDES
> > + case ANDESTECH_VENDOR_ID:
> > + cpu_mfr_info->patch_func = andes_errata_patch_func;
> > + break;
>
> and again alphabetical please
>
Oops I missed that, I'll sort this and all the above.

Cheers,
Prabhakar