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From: Conor Dooley <conor.dooley@microchip.com>
To: "Heiko Stübner" <heiko@sntech.de>
Cc: <linux-riscv@lists.infradead.org>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Andrew Jones <ajones@ventanamicro.com>,
	Guo Ren <guoren@kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order
Date: Thu, 24 Nov 2022 13:52:58 +0000	[thread overview]
Message-ID: <Y393OvlAa+h8Dyek@wendy> (raw)
In-Reply-To: <7034611.lOV4Wx5bFT@diego>

On Thu, Nov 24, 2022 at 02:42:20PM +0100, Heiko Stübner wrote:
> Am Donnerstag, 24. November 2022, 14:04:41 CET schrieb Conor Dooley:
> > I used the wikipedia table for ordering extensions when updating the
> > pattern here in foo.
> 
> 	    ^ foo? :-)

God damn it! I wrote foo, left nvim to check what the fixes tag would
be, came back and added it below but did not update this part of the
commit log...

> > Unfortunately that table did not match canonical order, as defined by
> > the RISC-V ISA Manual, which defines extension ordering in (what is
> > currently) Table 41, "Standard ISA extension names". Fix things up by
> > re-sorting v (vector) and adding p (packed-simd) & j (dynamic
> > languages). The e (reduced integer) and g (general) extensions are still
> > intentionally left out.
> > 
> > Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> > Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> 
> So I have compared the new pattern to the isa manual,
> and it looks like the order checks out, so
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Thanks!


  reply	other threads:[~2022-11-24 13:53 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-24 13:04 [PATCH 0/2] riscv,isa fixups Conor Dooley
2022-11-24 13:04 ` [PATCH 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions Conor Dooley
2022-11-25  1:12   ` Guo Ren
2022-11-24 13:04 ` [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Conor Dooley
2022-11-24 13:42   ` Heiko Stübner
2022-11-24 13:52     ` Conor Dooley [this message]
2022-11-28 17:41     ` Palmer Dabbelt
2022-11-28 18:08       ` Conor Dooley
2022-11-28 18:12         ` Palmer Dabbelt
2022-11-28 19:17           ` Conor Dooley
2022-11-28 23:41             ` Palmer Dabbelt
2022-11-29  5:19               ` Andrew Jones
2022-11-29 11:40                 ` Conor Dooley
2022-11-29 14:47                   ` [RFC 0/2] Putting some basic order on isa extension stuff Conor Dooley
2022-11-29 15:48                     ` Andrew Jones
2022-11-29 16:50                       ` Conor Dooley
2022-11-29 14:47                   ` [RFC 1/2] RISC-V: clarify ISA string ordering rules in cpu.c Conor Dooley
2022-11-29 16:12                     ` Andrew Jones
2022-11-29 16:54                       ` Conor Dooley
2022-11-29 17:19                         ` Andrew Jones
2022-11-29 17:48                           ` Conor Dooley
2022-11-29 14:47                   ` [RFC 2/2] RISC-V: resort all extensions in "canonical" order Conor Dooley
2022-11-29 16:35                     ` Andrew Jones
2022-12-01 13:51                   ` [PATCH] Documentation: riscv: note that counter access is part of the uABI Conor Dooley
2022-12-01 19:21                     ` Palmer Dabbelt
2022-12-03 10:38                       ` Jonathan Corbet
2022-12-03 10:45                         ` Jonathan Corbet
2022-12-03 10:56                           ` Conor Dooley
2023-01-09 21:36                             ` Atish Patra
2023-01-09 21:46                               ` Conor Dooley
2022-11-25  1:13   ` [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Guo Ren

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