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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id p2-20020a170902e74200b001869b988d93sm10093465plf.187.2022.11.15.07.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Nov 2022 07:29:48 -0800 (PST) Date: Tue, 15 Nov 2022 15:29:45 +0000 From: Sean Christopherson To: Xiaoyao Li Cc: Jiaxi Chen , kvm@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, pbonzini@redhat.com, ndesaulniers@google.com, alexandre.belloni@bootlin.com, peterz@infradead.org, jpoimboe@kernel.org, chang.seok.bae@intel.com, pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com, jmattson@google.com, sandipan.das@amd.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, fenghua.yu@intel.com, keescook@chromium.org, nathan@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/7] x86: KVM: Move existing x86 CPUID leaf [CPUID_7_1_EAX] to kvm-only leaf Message-ID: References: <20221110015252.202566-1-jiaxi.chen@linux.intel.com> <20221110015252.202566-2-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 15, 2022, Xiaoyao Li wrote: > On 11/10/2022 9:52 AM, Jiaxi Chen wrote: > > cpuid_leaf[12] CPUID_7_1_EAX has only two bits are in use currently: > > > > - AVX-VNNI CPUID.(EAX=7,ECX=1):EAX[bit 4] > > - AVX512-BF16 CPUID.(EAX=7,ECX=1):EAX[bit 5] > > > > These two bits have no other kernel usages other than the guest > > CPUID advertisement in KVM. Given that and to save space for kernel > > feature bits, move these two bits to the kvm-only subleaves. The > > existing leaf cpuid_leafs[12] is set to CPUID_LNX_5 so future feature > > can pick it. This basically reverts: > > > > - commit b85a0425d805 ("Enumerate AVX Vector Neural Network > > instructions") > > - commit b302e4b176d0 ("x86/cpufeatures: Enumerate the new AVX512 > > BFLOAT16 instructions") > > - commit 1085a6b585d7 ("KVM: Expose AVX_VNNI instruction to guset") > > FYI, LAM support has been queued in tip https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=aa387b1b1e666cacffc0b7ac7e0949a68013b2d9 > > It adds > > +#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ > > and conflict with this patch. > > Seen from the ISE, there are more bits defined in CPUID_7_1_EAX. And I > believe Intel will define more and it's likely some of them will be used by > kernel just like LAM. Heh, are any of the bits you believe Intel will add publicly documented? :-) LAM could be scattered, but if more bits are expected that's probably a waste of time and effort. Thanks for the heads up!