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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id h4-20020a05620a284400b006f9e103260dsm609831qkp.91.2022.11.17.07.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 07:25:37 -0800 (PST) Date: Thu, 17 Nov 2022 10:00:17 -0500 From: William Breathitt Gray To: Mark Brown Cc: linus.walleij@linaro.org, brgl@bgdev.pl, andriy.shevchenko@linux.intel.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, michael@walle.cc Subject: Re: [PATCH v2 2/4] regmap-irq: Add handle_mask_sync() callback Message-ID: References: <53e9e89cc9d7e9c20cbdfc13b360dcb43d07f832.1668129763.git.william.gray@linaro.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="pKPDdkdohjMYUtPY" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --pKPDdkdohjMYUtPY Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 15, 2022 at 05:14:14PM +0000, Mark Brown wrote: > On Thu, Nov 10, 2022 at 08:55:51PM -0500, William Breathitt Gray wrote: >=20 > > Provide a public callback handle_mask_sync() that drivers can use when > > they have more complex IRQ masking logic. The default implementation is > > regmap_irq_handle_mask_sync(), used if the chip doesn't provide its own > > callback. >=20 > Can you provide examples of something that would make sense to > open code in a driver rather than factoring out? It looks like > this has been added due to one of the devices you're looking at > for some reason disabling it's upstream interrupt when all of the > downstream interrupts are masked, while weird that doesn't seem > especally device specific. Sure, I actually intend to use this callback for the 104-idi-48 module as well in the v3 submission so I'll describe that situations well. For the 104-dio-48e we have the following: Base Address +B (Write): Enable Interrupt Base Address +B (Read): Disable Interrupt Base Address +F (Read/Write): Clear Interrupt So for 104-dio-48e, any write to 0xB will enable interrupts, while any read will disable interrupts; interrupts are with either a read or any write to 0xF. There's no status register either so software just has to assume that if an interrupt is raised then it was for the 104-dio-48e device. For the 104-idi-48, we do get a status register and some basic masking but it's broken down by banks rather than individual GPIO; there are six 8-bit banks (Port 0 Low Byte, Port 0 Mid Byte, Port 0 High Byte, Port 1 Low Byte, Port 1 Mid Byte, Port 1 High Byte): Base Address + 0 (Read/Write): Port 0 Low Byte Base Address + 1 (Read/Write): Port 0 Mid Byte Base Address + 2 (Read/Write): Port 0 High Byte Base Address + 3: N/A Base Address + 4 (Read/Write): Port 1 Low Byte Base Address + 5 (Read/Write): Port 1 Mid Byte Base Address + 6 (Read/Write): Port 1 High Byte Base Address + 7 (Read): IRQ Status Register/IRQ Clear Bit 0-5: Respective Bank IRQ Statuses Bit 6: IRQ Status (Active Low) Bit 7: IRQ Enable Status Base Address + 7 (Write): IRQ Enable/Disable Bit 0-5: Respective Bank IRQ Enable/Disable In this case, masking a bank will mask all 8 GPIO within that bank; so ideally I want a way to only mask a bank when all GPIO are masked, and unmasking when at least one is unmasked. Are there existing ways to support these kinds of configuration in regmap_irq? William Breathitt Gray --pKPDdkdohjMYUtPY Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCY3ZMgQAKCRC1SFbKvhIj K0tkAP0W7qrriEL+8XcqAtlCtVo5jH3iXr0hCdlvBlQ0qGpsQwD/YE6KpyUdScEb EpyPGmUgeR+FFhcDXh4ZxmnoBZXgWQE= =EmJX -----END PGP SIGNATURE----- --pKPDdkdohjMYUtPY--