From: Sean Christopherson <seanjc@google.com>
To: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Cc: kvm@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org,
hpa@zytor.com, pbonzini@redhat.com, ndesaulniers@google.com,
alexandre.belloni@bootlin.com, peterz@infradead.org,
jpoimboe@kernel.org, chang.seok.bae@intel.com,
pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com,
jmattson@google.com, sandipan.das@amd.com, tony.luck@intel.com,
sathyanarayanan.kuppuswamy@linux.intel.com, fenghua.yu@intel.com,
keescook@chromium.org, nathan@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 3/6] x86: KVM: Advertise AVX-IFMA CPUID to user space
Date: Fri, 18 Nov 2022 16:08:25 +0000 [thread overview]
Message-ID: <Y3et+VpYh+L7N8SL@google.com> (raw)
In-Reply-To: <20221118141509.489359-4-jiaxi.chen@linux.intel.com>
On Fri, Nov 18, 2022, Jiaxi Chen wrote:
> AVX-IFMA is a new instruction in the latest Intel platform Sierra
> Forest. This instruction packed multiplies unsigned 52-bit integers and
> adds the low/high 52-bit products to Qword Accumulators.
>
> The bit definition:
> CPUID.(EAX=7,ECX=1):EAX[bit 23]
>
> This CPUID is exposed to user space. Besides, there is no other VMX
> control for this instruction.
>
> Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/kvm/cpuid.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index df4a7f7505a9..159f8b9898bf 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -310,6 +310,7 @@
> #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
> #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */
> #define X86_FEATURE_AMX_FP16 (12*32+21) /* AMX fp16 Support */
> +#define X86_FEATURE_AVX_IFMA (12*32+23) /* Support for VPMADD52[H,L]UQ */
>
> /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
> #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 2a334d4cd04e..5726afb2d14c 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -657,8 +657,8 @@ void kvm_set_cpu_caps(void)
> kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
>
> kvm_cpu_cap_mask(CPUID_7_1_EAX,
> - F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16)
> - );
> + F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16) |
> + F(AVX_IFMA));
Please keep the terminating paranthesis+semicolon on a separate line. KVM isn't
100% consistent (as usual), but I would rather "fix" the cases that don't put
the terminators on their own line.
next prev parent reply other threads:[~2022-11-18 16:08 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-18 14:15 [PATCH v4 0/6] x86: KVM: Advertise CPUID of new Intel platform instructions to user space Jiaxi Chen
2022-11-18 14:15 ` [PATCH v4 1/6] x86: KVM: Advertise CMPccXADD CPUID " Jiaxi Chen
2022-11-18 16:47 ` Dave Hansen
2022-11-18 18:34 ` Borislav Petkov
2022-11-21 14:46 ` Jiaxi Chen
2022-11-21 15:29 ` Dave Hansen
2022-11-21 15:48 ` Sean Christopherson
2022-11-21 15:53 ` Borislav Petkov
2022-11-21 17:28 ` Sean Christopherson
2022-11-21 19:50 ` Borislav Petkov
2022-11-23 6:33 ` Jiaxi Chen
2022-11-21 15:38 ` Borislav Petkov
2022-11-23 7:46 ` Jiaxi Chen
2022-11-18 14:15 ` [PATCH v4 2/6] x86: KVM: Advertise AMX-FP16 " Jiaxi Chen
2022-11-18 14:15 ` [PATCH v4 3/6] x86: KVM: Advertise AVX-IFMA " Jiaxi Chen
2022-11-18 16:08 ` Sean Christopherson [this message]
2022-11-21 14:46 ` Jiaxi Chen
2022-11-18 14:15 ` [PATCH v4 4/6] x86: KVM: Advertise AVX-VNNI-INT8 " Jiaxi Chen
2022-11-18 17:17 ` Sean Christopherson
2022-11-21 15:06 ` Jiaxi Chen
2022-11-18 14:15 ` [PATCH v4 5/6] x86: KVM: Advertise AVX-NE-CONVERT " Jiaxi Chen
2022-11-18 14:15 ` [PATCH v4 6/6] x86: KVM: Advertise PREFETCHIT0/1 " Jiaxi Chen
2022-11-18 15:11 ` [PATCH v4 0/6] x86: KVM: Advertise CPUID of new Intel platform instructions " Borislav Petkov
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