From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 752B8C46467 for ; Mon, 28 Nov 2022 23:51:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234800AbiK1XvR (ORCPT ); Mon, 28 Nov 2022 18:51:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234790AbiK1XvP (ORCPT ); Mon, 28 Nov 2022 18:51:15 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55B5028E36 for ; Mon, 28 Nov 2022 15:51:14 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id d18so967297pls.4 for ; Mon, 28 Nov 2022 15:51:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=oVgoeAVnfsk2iXYG0JTdu0THjStYeYpgj9cQZUW7cks=; b=ZWgV6HJIMapNybCv4vR6zXDsW6Z7GIO+i/wZEeRsIK8vPOSFXAioyWuCwuOKWrl5yD Nni6kSMkTP5RwO4ue+RjMY/l20JLoL+rB8a92x1ucdJjD+orCMDfUTWPyfhAJ9KfOmbK BxW2kgEhqa+jUNkXQoPBqUjp4hjnhUjT6Pxq9J+3TAdFvSqxKnsnF83lek83CJTdfGoH 6+mljQF+SC5lQ+cNDQ13IXoDXg3ExOEVH/sUG2CIfrYPoi1cMTzbWraOOI0pbFb3fAVy cFzEpEmy7dGhKyQhZRampL5tVSD+egmW/f9LgGTnIWfRKZzxas6kkiv6RMa77MYEZhKn l/hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=oVgoeAVnfsk2iXYG0JTdu0THjStYeYpgj9cQZUW7cks=; b=nExUju5+ulvtdpxmcj0R2cE1kySdS8QumXArz8VuAXpVP9alyPpEAuDH4eRNJj2Buu puhpe4ExYaofggwiet4uM0n7VGd8YGWFMkMe9kQKcYLubinl9wcvfF4FN18EBcYCn3rv 9wlN0Hio55XXTn2IbX2RXuKsYSpWtq76RPWhDrDBqRQmmrM3/v4IwP3xi1dLXs3fuwYz WxzhJZRLx1bnCkCsAahjnJUbjUDaH1M+8vIETXG/PtaW/QJqbpNnrSh73eQYEtM8kAtm XqBkaUr/p3D1UmdHwPsGaGnNRpMaHu91Jy7I6grSApJSF7STuBSxTgClI7atIpalPbaJ Duow== X-Gm-Message-State: ANoB5pnIfMTGR3rmMuwQ6saJotYkTvVQTgUwKUNN0Vg0k7eFJCFiVm6E Pc8ciqbuAolV/D90/RCNdEoXCw== X-Google-Smtp-Source: AA0mqf4NTXD1EHu2Cevt0auVcetSPnQ6e77T7FE4dlWd2ySwt8m5T4jr2ialJIYYV92GIt+aZwM2Gg== X-Received: by 2002:a17:902:7688:b0:186:971b:b7e5 with SMTP id m8-20020a170902768800b00186971bb7e5mr49187518pll.54.1669679473706; Mon, 28 Nov 2022 15:51:13 -0800 (PST) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id 123-20020a630781000000b00470275c8d6dsm7159081pgh.10.2022.11.28.15.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 15:51:13 -0800 (PST) Date: Mon, 28 Nov 2022 23:51:09 +0000 From: Sean Christopherson To: Isaku Yamahata Cc: "Huang, Kai" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "Yamahata, Isaku" , "pbonzini@redhat.com" , "Shahar, Sagi" , "Aktas, Erdem" , "dmatlack@google.com" Subject: Re: [PATCH v10 034/108] KVM: x86/mmu: Add Suppress VE bit to shadow_mmio_{value, mask} Message-ID: References: <1c480a48c2697054b1cfe068fa073f4035648f9a.1667110240.git.isaku.yamahata@intel.com> <20221117180220.GJ2350331@ls.amr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20221117180220.GJ2350331@ls.amr.corp.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 17, 2022, Isaku Yamahata wrote: > On Wed, Nov 09, 2022 at 11:48:30AM +0000, > "Huang, Kai" wrote: > > > On Sat, 2022-10-29 at 23:22 -0700, isaku.yamahata@intel.com wrote: > > > From: Isaku Yamahata > > > > > > Because TDX will need shadow_mmio_mask to be VMX_SUPPRESS_VE | RWX > > > shadow_mmio_value to be 0, make VMX EPT case use same value for TDX > > > shadow_mmio_mask.   > > > > > > > TDX need to use different mmio_mask/value doesn't mean they need to be changed > > for VMX guest. I think the true purpose here is to still be able to use a > > global shadow_mmio_mask for both TDX and VMX guests. So please explicitly call > > out. > > That's right. With this change, per-VM shadow_mmio_{value, mask} can be avoided. > The common value can be used for both VMX and TDX. No, the mask can be global, but the value needs to be per-VM. VMX needs to generate an EPT misconfig, but TDX needs to generate an EPT violation to get the automagic #VE reflection.