Re: [PATCH net-next 2/4] phylib: Add support for 10BASE-T1S link modes and PLCA config

[Piergiorgio Beruto <piergiorgio.beruto@gmail.com>]

On Sun, Dec 04, 2022 at 04:45:22PM +0000, Russell King (Oracle) wrote:
> Hi,
> 
> On Sun, Dec 04, 2022 at 03:30:52AM +0100, Piergiorgio Beruto wrote:
> > diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
> > index 5d08c627a516..5d8085fffffc 100644
> > --- a/drivers/net/phy/phy-core.c
> > +++ b/drivers/net/phy/phy-core.c
> > @@ -13,7 +13,7 @@
> >   */
> >  const char *phy_speed_to_str(int speed)
> >  {
> > -	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 99,
> > +	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 102,
> >  		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
> >  		"If a speed or mode has been added please update phy_speed_to_str "
> >  		"and the PHY settings array.\n");
> 
> I think you need to update settings[] in this file as well.
Oh, sure. I've just added the following:

	PHY_SETTING(     10, FULL,     10baseT1S_Full		),
	PHY_SETTING(     10, HALF,     10baseT1S_Half		),
	PHY_SETTING(     10, HALF,     10baseT1S_P2MP_Half	),

I will amend the patch after I reviewed all the feedback.

Thanks,
Piergiorgio