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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id f17-20020a170902f39100b00178b9c997e5sm14769739ple.138.2022.12.07.08.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 08:31:33 -0800 (PST) Date: Wed, 7 Dec 2022 16:31:30 +0000 From: Sean Christopherson To: Atish Patra Cc: Atish Patra , linux-kernel@vger.kernel.org, Albert Ou , Anup Patel , Guo Ren , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: Re: [RFC 8/9] RISC-V: KVM: Implement perf support Message-ID: References: <20220718170205.2972215-1-atishp@rivosinc.com> <20220718170205.2972215-9-atishp@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 07, 2022, Atish Patra wrote: > On Fri, Dec 2, 2022 at 9:09 AM Sean Christopherson wrote: > > > > On Mon, Jul 18, 2022, Atish Patra wrote: > > > RISC-V SBI PMU & Sscofpmf ISA extension allows supporting perf in > > > the virtualization enviornment as well. KVM implementation > > > relies on SBI PMU extension for most of the part while traps > > > & emulates the CSRs read for counter access. > > > > For the benefit of non-RISCV people, the changelog (and documentation?) should > > explain why RISC-V doesn't need to tap into kvm_register_perf_callbacks(). > > As per my understanding, kvm_register_perf_callbacks is only useful > during event sampling for guests. Please let me know if I missed > something. > This series doesn't support sampling and guest counter overflow interrupt yet. > That's why kvm_register_perf_callbacks support is missing. Ah, I missed that connection in the cover letter. In the future, if a patch adds partial support for a thing/feature, it's very helpful to call that out in the lack shortlog and changelog, even for RFCs. E.g. adding a single word in the shortlog and sentence or two in the changelog doesn't take much time on your end, and helps avoid cases like this where drive-by reviewers like me from cause a fuss about non-issues. RISC-V: KVM: Implement partial perf support ... Counter overflow and interrupts are not supported as the relevant architectural specifications are still under discussion. Thanks!