Re: [PATCH 1/4] arm64: dts: qcom: sc8280xp: rename i2c5 to i2c21

Konrad Dybcio
2022-12-12T18:52:00Z

On 12.12.2022 19:23, Brian Masney wrote:
> According to the downstream 5.4 kernel sources for the sa8540p,
> i2c@894000 is labeled i2c bus 21, not 5. The interrupts and clocks
> also match. Let's go ahead and correct the name that's used in the
> three files where this is listed.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> Fixes: 152d1faf1e2f3 ("arm64: dts: qcom: add SC8280XP platform")
> Fixes: ccd3517faf183 ("arm64: dts: qcom: sc8280xp: Add reference device")
> Fixes: 32c231385ed43 ("arm64: dts: qcom: sc8280xp: add Lenovo Thinkpad X13s devicetree")
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 6 +++---
> arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 +++---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 551768f97729..1ab76724144d 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -326,11 +326,11 @@ &qup2 {
> status = "okay";
> };
>
> -&qup2_i2c5 {
> +&qup2_i2c21 {
> clock-frequency = <400000>;
>
> pinctrl-names = "default";
> - pinctrl-0 = <&qup2_i2c5_default>;
> + pinctrl-0 = <&qup2_i2c21_default>;
>
> status = "okay";
>
> @@ -598,7 +598,7 @@ qup0_i2c4_default: qup0-i2c4-default-state {
> drive-strength = <16>;
> };
>
> - qup2_i2c5_default: qup2-i2c5-default-state {
> + qup2_i2c21_default: qup2-i2c21-default-state {
> pins = "gpio81", "gpio82";
> function = "qup21";
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> index 568c6be1ceaa..284adf60386a 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> @@ -531,11 +531,11 @@ &qup2 {
> status = "okay";
> };
>
> -&qup2_i2c5 {
> +&qup2_i2c21 {
> clock-frequency = <400000>;
>
> pinctrl-names = "default";
> - pinctrl-0 = <&qup2_i2c5_default>;
> + pinctrl-0 = <&qup2_i2c21_default>;
>
> status = "okay";
>
> @@ -801,7 +801,7 @@ qup0_i2c4_default: qup0-i2c4-default-state {
> drive-strength = <16>;
> };
>
> - qup2_i2c5_default: qup2-i2c5-default-state {
> + qup2_i2c21_default: qup2-i2c21-default-state {
> pins = "gpio81", "gpio82";
> function = "qup21";
> bias-disable;
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 109c9d2b684d..875cc91324ce 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -827,7 +827,7 @@ qup2_uart17: serial@884000 {
> status = "disabled";
> };
>
> - qup2_i2c5: i2c@894000 {
> + qup2_i2c21: i2c@894000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00894000 0 0x4000>;
> clock-names = "se";