* [PATCH v3 1/3] serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h
2022-12-09 15:04 [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Bin Meng
@ 2022-12-09 15:04 ` Bin Meng
2022-12-09 15:04 ` [PATCH v3 2/3] riscv: Implement semihost.h for earlycon semihost driver Bin Meng
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-12-09 15:04 UTC (permalink / raw)
To: linux-kernel, linux-riscv, linux-serial
Cc: Catalin Marinas, Greg Kroah-Hartman, Jiri Slaby, Russell King,
Will Deacon, linux-arm-kernel
Move smh_putc() variants in respective arch/*/include/asm/semihost.h,
in preparation to add RISC-V support.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
Changes in v3:
- add #ifdef in the header to prevent from multiple inclusion
- add forward-declare struct uart_port
Changes in v2:
- new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h"
arch/arm/include/asm/semihost.h | 30 ++++++++++++++++++++++
arch/arm64/include/asm/semihost.h | 24 +++++++++++++++++
drivers/tty/serial/earlycon-arm-semihost.c | 25 +-----------------
3 files changed, 55 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/include/asm/semihost.h
create mode 100644 arch/arm64/include/asm/semihost.h
diff --git a/arch/arm/include/asm/semihost.h b/arch/arm/include/asm/semihost.h
new file mode 100644
index 000000000000..f365787e7c23
--- /dev/null
+++ b/arch/arm/include/asm/semihost.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Adapted for ARM and earlycon:
+ * Copyright (C) 2014 Linaro Ltd.
+ * Author: Rob Herring <robh@kernel.org>
+ */
+
+#ifndef _ARM_SEMIHOST_H_
+#define _ARM_SEMIHOST_H_
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define SEMIHOST_SWI "0xab"
+#else
+#define SEMIHOST_SWI "0x123456"
+#endif
+
+struct uart_port;
+
+static inline void smh_putc(struct uart_port *port, unsigned char c)
+{
+ asm volatile("mov r1, %0\n"
+ "mov r0, #3\n"
+ "svc " SEMIHOST_SWI "\n"
+ : : "r" (&c) : "r0", "r1", "memory");
+}
+
+#endif /* _ARM_SEMIHOST_H_ */
diff --git a/arch/arm64/include/asm/semihost.h b/arch/arm64/include/asm/semihost.h
new file mode 100644
index 000000000000..87e353dab868
--- /dev/null
+++ b/arch/arm64/include/asm/semihost.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Adapted for ARM and earlycon:
+ * Copyright (C) 2014 Linaro Ltd.
+ * Author: Rob Herring <robh@kernel.org>
+ */
+
+#ifndef _ARM64_SEMIHOST_H_
+#define _ARM64_SEMIHOST_H_
+
+struct uart_port;
+
+static inline void smh_putc(struct uart_port *port, unsigned char c)
+{
+ asm volatile("mov x1, %0\n"
+ "mov x0, #3\n"
+ "hlt 0xf000\n"
+ : : "r" (&c) : "x0", "x1", "memory");
+}
+
+#endif /* _ARM64_SEMIHOST_H_ */
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c
index fcdec5f42376..e4692a8433f9 100644
--- a/drivers/tty/serial/earlycon-arm-semihost.c
+++ b/drivers/tty/serial/earlycon-arm-semihost.c
@@ -11,30 +11,7 @@
#include <linux/console.h>
#include <linux/init.h>
#include <linux/serial_core.h>
-
-#ifdef CONFIG_THUMB2_KERNEL
-#define SEMIHOST_SWI "0xab"
-#else
-#define SEMIHOST_SWI "0x123456"
-#endif
-
-/*
- * Semihosting-based debug console
- */
-static void smh_putc(struct uart_port *port, unsigned char c)
-{
-#ifdef CONFIG_ARM64
- asm volatile("mov x1, %0\n"
- "mov x0, #3\n"
- "hlt 0xf000\n"
- : : "r" (&c) : "x0", "x1", "memory");
-#else
- asm volatile("mov r1, %0\n"
- "mov r0, #3\n"
- "svc " SEMIHOST_SWI "\n"
- : : "r" (&c) : "r0", "r1", "memory");
-#endif
-}
+#include <asm/semihost.h>
static void smh_write(struct console *con, const char *s, unsigned n)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 2/3] riscv: Implement semihost.h for earlycon semihost driver
2022-12-09 15:04 [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Bin Meng
2022-12-09 15:04 ` [PATCH v3 1/3] serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h Bin Meng
@ 2022-12-09 15:04 ` Bin Meng
2022-12-09 15:04 ` [PATCH v3 3/3] serial: Rename " Bin Meng
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-12-09 15:04 UTC (permalink / raw)
To: linux-kernel, linux-riscv, linux-serial
Cc: Albert Ou, Greg Kroah-Hartman, Jiri Slaby, Palmer Dabbelt,
Paul Walmsley
Per RISC-V semihosting spec [1], implement semihost.h for the existing
Arm semihosting earlycon driver to work on RISC-V.
Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1]
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
Changes in v3:
- add #ifdef in the header to prevent from multiple inclusion
- add forward-declare struct uart_port
- add a Link tag in the commit message
Changes in v2:
- Move the RISC-V implementation to semihost.h
arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++++++++++++
drivers/tty/serial/Kconfig | 2 +-
2 files changed, 27 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/include/asm/semihost.h
diff --git a/arch/riscv/include/asm/semihost.h b/arch/riscv/include/asm/semihost.h
new file mode 100644
index 000000000000..557a34938193
--- /dev/null
+++ b/arch/riscv/include/asm/semihost.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 tinylab.org
+ * Author: Bin Meng <bmeng@tinylab.org>
+ */
+
+#ifndef _RISCV_SEMIHOST_H_
+#define _RISCV_SEMIHOST_H_
+
+struct uart_port;
+
+static inline void smh_putc(struct uart_port *port, unsigned char c)
+{
+ asm volatile("addi a1, %0, 0\n"
+ "addi a0, zero, 3\n"
+ ".balign 16\n"
+ ".option push\n"
+ ".option norvc\n"
+ "slli zero, zero, 0x1f\n"
+ "ebreak\n"
+ "srai zero, zero, 0x7\n"
+ ".option pop\n"
+ : : "r" (&c) : "a0", "a1", "memory");
+}
+
+#endif /* _RISCV_SEMIHOST_H_ */
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 434f83168546..e94d1265151c 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE
config SERIAL_EARLYCON_ARM_SEMIHOST
bool "Early console using ARM semihosting"
- depends on ARM64 || ARM
+ depends on ARM64 || ARM || RISCV
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 3/3] serial: Rename earlycon semihost driver
2022-12-09 15:04 [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Bin Meng
2022-12-09 15:04 ` [PATCH v3 1/3] serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h Bin Meng
2022-12-09 15:04 ` [PATCH v3 2/3] riscv: Implement semihost.h for earlycon semihost driver Bin Meng
@ 2022-12-09 15:04 ` Bin Meng
2022-12-21 15:51 ` [PATCH v3 0/3] serial: Add RISC-V support to the " Bin Meng
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-12-09 15:04 UTC (permalink / raw)
To: linux-kernel, linux-riscv, linux-serial; +Cc: Greg Kroah-Hartman, Jiri Slaby
Now that earlycon semihost driver works on RISC-V too, let's use a
much more generic name for the driver.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
(no changes since v1)
drivers/tty/serial/Kconfig | 12 ++++++------
drivers/tty/serial/Makefile | 2 +-
.../{earlycon-arm-semihost.c => earlycon-semihost.c} | 0
3 files changed, 7 insertions(+), 7 deletions(-)
rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (100%)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index e94d1265151c..a3779472edf6 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -73,17 +73,17 @@ config SERIAL_AMBA_PL011_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
-config SERIAL_EARLYCON_ARM_SEMIHOST
- bool "Early console using ARM semihosting"
+config SERIAL_EARLYCON_SEMIHOST
+ bool "Early console using Arm compatible semihosting"
depends on ARM64 || ARM || RISCV
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
help
- Support for early debug console using ARM semihosting. This enables
- the console before standard serial driver is probed. This is enabled
- with "earlycon=smh" on the kernel command line. The console is
- enabled when early_param is processed.
+ Support for early debug console using Arm compatible semihosting.
+ This enables the console before standard serial driver is probed.
+ This is enabled with "earlycon=smh" on the kernel command line.
+ The console is enabled when early_param is processed.
config SERIAL_EARLYCON_RISCV_SBI
bool "Early console using RISC-V SBI"
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 238a9557b487..cd9afd9e3018 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -6,7 +6,7 @@
obj-$(CONFIG_SERIAL_CORE) += serial_core.o
obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
-obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o
+obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o
obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o
# These Sparc drivers have to appear before others such as 8250
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-semihost.c
similarity index 100%
rename from drivers/tty/serial/earlycon-arm-semihost.c
rename to drivers/tty/serial/earlycon-semihost.c
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver
2022-12-09 15:04 [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Bin Meng
` (2 preceding siblings ...)
2022-12-09 15:04 ` [PATCH v3 3/3] serial: Rename " Bin Meng
@ 2022-12-21 15:51 ` Bin Meng
2022-12-21 16:09 ` gregkh
2022-12-22 20:06 ` Sergey Matyukevich
2022-12-29 16:22 ` Palmer Dabbelt
5 siblings, 1 reply; 9+ messages in thread
From: Bin Meng @ 2022-12-21 15:51 UTC (permalink / raw)
To: linux-kernel, linux-riscv, linux-serial
Cc: aou, catalin.marinas, gregkh, jirislaby, palmer, paul.walmsley,
linux, will, linux-arm-kernel
On 2022/12/9 23:04:34, "Bin Meng" <bmeng@tinylab.org> wrote:
>RISC-V semihosting spec [1] is built on top of the existing Arm one;
>we can add RISC-V earlycon semihost driver easily.
>
>This series refactors the existing driver a little bit, to move smh_putc()
>variants in respective arch's semihost.h, then we can implement RISC-V's
>version in the riscv arch directory.
>
>Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1]
>
>Changes in v3:
>- add #ifdef in the header to prevent from multiple inclusion
>- add forward-declare struct uart_port
>- add a Link tag in the commit message
>
Ping?
Regards,
Bin
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver
2022-12-21 15:51 ` [PATCH v3 0/3] serial: Add RISC-V support to the " Bin Meng
@ 2022-12-21 16:09 ` gregkh
0 siblings, 0 replies; 9+ messages in thread
From: gregkh @ 2022-12-21 16:09 UTC (permalink / raw)
To: Bin Meng
Cc: linux-kernel, linux-riscv, linux-serial, aou, catalin.marinas,
jirislaby, palmer, paul.walmsley, linux, will, linux-arm-kernel
On Wed, Dec 21, 2022 at 03:51:59PM +0000, Bin Meng wrote:
> On 2022/12/9 23:04:34, "Bin Meng" <bmeng@tinylab.org> wrote:
>
> > RISC-V semihosting spec [1] is built on top of the existing Arm one;
> > we can add RISC-V earlycon semihost driver easily.
> >
> > This series refactors the existing driver a little bit, to move smh_putc()
> > variants in respective arch's semihost.h, then we can implement RISC-V's
> > version in the riscv arch directory.
> >
> > Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1]
> >
> > Changes in v3:
> > - add #ifdef in the header to prevent from multiple inclusion
> > - add forward-declare struct uart_port
> > - add a Link tag in the commit message
> >
> Ping?
It is the middle of the merge window, we can not do anything until after
6.2-rc1 is out, please be patient.
While you wait, please take the time to review other patches on the
mailing list to help with the workload of the maintainers.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver
2022-12-09 15:04 [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Bin Meng
` (3 preceding siblings ...)
2022-12-21 15:51 ` [PATCH v3 0/3] serial: Add RISC-V support to the " Bin Meng
@ 2022-12-22 20:06 ` Sergey Matyukevich
2022-12-23 9:11 ` Bin Meng
2022-12-29 16:22 ` Palmer Dabbelt
5 siblings, 1 reply; 9+ messages in thread
From: Sergey Matyukevich @ 2022-12-22 20:06 UTC (permalink / raw)
To: Bin Meng
Cc: linux-kernel, linux-riscv, linux-serial, Albert Ou,
Catalin Marinas, Greg Kroah-Hartman, Jiri Slaby, Palmer Dabbelt,
Paul Walmsley, Russell King, Will Deacon, linux-arm-kernel
Hi Bin,
> RISC-V semihosting spec [1] is built on top of the existing Arm one;
> we can add RISC-V earlycon semihost driver easily.
>
> This series refactors the existing driver a little bit, to move smh_putc()
> variants in respective arch's semihost.h, then we can implement RISC-V's
> version in the riscv arch directory.
>
> Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1]
>
> Changes in v3:
> - add #ifdef in the header to prevent from multiple inclusion
> - add forward-declare struct uart_port
> - add a Link tag in the commit message
>
> Changes in v2:
> - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h"
> - Move the RISC-V implementation to semihost.h
>
> Bin Meng (3):
> serial: earlycon-arm-semihost: Move smh_putc() variants in respective
> arch's semihost.h
> riscv: Implement semihost.h for earlycon semihost driver
> serial: Rename earlycon semihost driver
>
> arch/arm/include/asm/semihost.h | 30 +++++++++++++++++++
> arch/arm64/include/asm/semihost.h | 24 +++++++++++++++
> arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++
> drivers/tty/serial/Kconfig | 14 ++++-----
> drivers/tty/serial/Makefile | 2 +-
> ...con-arm-semihost.c => earlycon-semihost.c} | 25 +---------------
> 6 files changed, 89 insertions(+), 32 deletions(-)
> create mode 100644 arch/arm/include/asm/semihost.h
> create mode 100644 arch/arm64/include/asm/semihost.h
> create mode 100644 arch/riscv/include/asm/semihost.h
> rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (57%)
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Applied the patches on top of Linux 6.1 and tested earlycon logs from
RISC-V target in OpenOCD.
Regards,
Sergey
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver
2022-12-22 20:06 ` Sergey Matyukevich
@ 2022-12-23 9:11 ` Bin Meng
0 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-12-23 9:11 UTC (permalink / raw)
To: Sergey Matyukevich
Cc: linux-kernel, linux-riscv, linux-serial, aou, catalin.marinas,
gregkh, jirislaby, palmer, paul.walmsley, linux, will,
linux-arm-kernel
Hi Sergey,
On 2022/12/23 4:06:23, "Sergey Matyukevich" <geomatsi@gmail.com> wrote:
>Hi Bin,
>
>> RISC-V semihosting spec [1] is built on top of the existing Arm one;
>> we can add RISC-V earlycon semihost driver easily.
>>
>> This series refactors the existing driver a little bit, to move smh_putc()
>> variants in respective arch's semihost.h, then we can implement RISC-V's
>> version in the riscv arch directory.
>>
>> Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1]
>>
>> Changes in v3:
>> - add #ifdef in the header to prevent from multiple inclusion
>> - add forward-declare struct uart_port
>> - add a Link tag in the commit message
>>
>> Changes in v2:
>> - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h"
>> - Move the RISC-V implementation to semihost.h
>>
>> Bin Meng (3):
>> serial: earlycon-arm-semihost: Move smh_putc() variants in respective
>> arch's semihost.h
>> riscv: Implement semihost.h for earlycon semihost driver
>> serial: Rename earlycon semihost driver
>>
>> arch/arm/include/asm/semihost.h | 30 +++++++++++++++++++
>> arch/arm64/include/asm/semihost.h | 24 +++++++++++++++
>> arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++
>> drivers/tty/serial/Kconfig | 14 ++++-----
>> drivers/tty/serial/Makefile | 2 +-
>> ...con-arm-semihost.c => earlycon-semihost.c} | 25 +---------------
>> 6 files changed, 89 insertions(+), 32 deletions(-)
>> create mode 100644 arch/arm/include/asm/semihost.h
>> create mode 100644 arch/arm64/include/asm/semihost.h
>> create mode 100644 arch/riscv/include/asm/semihost.h
>> rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (57%)
>
>Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
>
>Applied the patches on top of Linux 6.1 and tested earlycon logs from
>RISC-V target in OpenOCD.
>
Thanks for your testing!
Regards,
Bin
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver
2022-12-09 15:04 [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Bin Meng
` (4 preceding siblings ...)
2022-12-22 20:06 ` Sergey Matyukevich
@ 2022-12-29 16:22 ` Palmer Dabbelt
5 siblings, 0 replies; 9+ messages in thread
From: Palmer Dabbelt @ 2022-12-29 16:22 UTC (permalink / raw)
To: bmeng
Cc: linux-kernel, linux-riscv, linux-serial, aou, catalin.marinas,
Greg KH, jirislaby, Paul Walmsley, linux, Will Deacon,
linux-arm-kernel
On Fri, 09 Dec 2022 07:04:34 PST (-0800), bmeng@tinylab.org wrote:
>
> RISC-V semihosting spec [1] is built on top of the existing Arm one;
> we can add RISC-V earlycon semihost driver easily.
>
> This series refactors the existing driver a little bit, to move smh_putc()
> variants in respective arch's semihost.h, then we can implement RISC-V's
> version in the riscv arch directory.
>
> Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1]
>
> Changes in v3:
> - add #ifdef in the header to prevent from multiple inclusion
> - add forward-declare struct uart_port
> - add a Link tag in the commit message
>
> Changes in v2:
> - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h"
> - Move the RISC-V implementation to semihost.h
>
> Bin Meng (3):
> serial: earlycon-arm-semihost: Move smh_putc() variants in respective
> arch's semihost.h
> riscv: Implement semihost.h for earlycon semihost driver
> serial: Rename earlycon semihost driver
>
> arch/arm/include/asm/semihost.h | 30 +++++++++++++++++++
> arch/arm64/include/asm/semihost.h | 24 +++++++++++++++
> arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++
> drivers/tty/serial/Kconfig | 14 ++++-----
> drivers/tty/serial/Makefile | 2 +-
> ...con-arm-semihost.c => earlycon-semihost.c} | 25 +---------------
> 6 files changed, 89 insertions(+), 32 deletions(-)
> create mode 100644 arch/arm/include/asm/semihost.h
> create mode 100644 arch/arm64/include/asm/semihost.h
> create mode 100644 arch/riscv/include/asm/semihost.h
> rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (57%)
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
^ permalink raw reply [flat|nested] 9+ messages in thread