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Thu, 22 Dec 2022 12:06:25 -0800 (PST) Received: from curiosity ([5.188.167.245]) by smtp.gmail.com with ESMTPSA id y11-20020a19750b000000b004b4b0a68f67sm184767lfe.185.2022.12.22.12.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 12:06:24 -0800 (PST) Date: Thu, 22 Dec 2022 23:06:23 +0300 From: Sergey Matyukevich To: Bin Meng Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, Albert Ou , Catalin Marinas , Greg Kroah-Hartman , Jiri Slaby , Palmer Dabbelt , Paul Walmsley , Russell King , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Message-ID: References: <20221209150437.795918-1-bmeng@tinylab.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221209150437.795918-1-bmeng@tinylab.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bin, > RISC-V semihosting spec [1] is built on top of the existing Arm one; > we can add RISC-V earlycon semihost driver easily. > > This series refactors the existing driver a little bit, to move smh_putc() > variants in respective arch's semihost.h, then we can implement RISC-V's > version in the riscv arch directory. > > Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] > > Changes in v3: > - add #ifdef in the header to prevent from multiple inclusion > - add forward-declare struct uart_port > - add a Link tag in the commit message > > Changes in v2: > - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h" > - Move the RISC-V implementation to semihost.h > > Bin Meng (3): > serial: earlycon-arm-semihost: Move smh_putc() variants in respective > arch's semihost.h > riscv: Implement semihost.h for earlycon semihost driver > serial: Rename earlycon semihost driver > > arch/arm/include/asm/semihost.h | 30 +++++++++++++++++++ > arch/arm64/include/asm/semihost.h | 24 +++++++++++++++ > arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++ > drivers/tty/serial/Kconfig | 14 ++++----- > drivers/tty/serial/Makefile | 2 +- > ...con-arm-semihost.c => earlycon-semihost.c} | 25 +--------------- > 6 files changed, 89 insertions(+), 32 deletions(-) > create mode 100644 arch/arm/include/asm/semihost.h > create mode 100644 arch/arm64/include/asm/semihost.h > create mode 100644 arch/riscv/include/asm/semihost.h > rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (57%) Tested-by: Sergey Matyukevich Applied the patches on top of Linux 6.1 and tested earlycon logs from RISC-V target in OpenOCD. Regards, Sergey