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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: matthew.gerlach@linux.intel.com
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
	basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
	mdf@kernel.org, linux-fpga@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	tianfei.zhang@intel.com, corbet@lwn.net,
	gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
	jirislaby@kernel.org, geert+renesas@glider.be,
	niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
	johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com,
	marpagan@redhat.com, bagasdotme@gmail.com
Subject: Re: [PATCH v10 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550.
Date: Tue, 10 Jan 2023 12:32:12 +0200	[thread overview]
Message-ID: <Y70+rAq1QoS4ohdG@smile.fi.intel.com> (raw)
In-Reply-To: <20230110003029.806022-5-matthew.gerlach@linux.intel.com>

On Mon, Jan 09, 2023 at 04:30:29PM -0800, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> Add a Device Feature List (DFL) bus driver for the Altera
> 16550 implementation of UART.

...

> +static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval)
> +{
> +	size_t psize;
> +	u64 *p;
> +
> +	p = dfh_find_param(dfl_dev, param_id, &psize);
> +	if (IS_ERR(p))
> +		return PTR_ERR(p);

> +	if (psize != sizeof(u64))
> +		return -EINVAL;

If this code stays in the newer versions, make it more robust against changes,
i.e. by using sizeof(*pval).

> +	*pval = *p;
> +
> +	return 0;
> +}

...

> +config SERIAL_8250_DFL
> +	tristate "DFL bus driver for Altera 16550 UART"

5

> +	depends on SERIAL_8250 && FPGA_DFL
> +	help
> +	  This option enables support for a Device Feature List (DFL) bus
> +	  driver for the Altera 16650 UART. One or more Altera 16650 UARTs

6

Which one is correct?

> +	  can be instantiated in a FPGA and then be discovered during
> +	  enumeration of the DFL bus.
> +
> +	  To compile this driver as a module, chose M here: the
> +	  module will be called 8250_dfl.

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2023-01-10 10:33 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-10  0:30 [PATCH v10 0/4] Enhance definition of DFH and use enhancements for UART driver matthew.gerlach
2023-01-10  0:30 ` [PATCH v10 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2023-01-10  0:30 ` [PATCH v10 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2023-01-10  0:30 ` [PATCH v10 3/4] fpga: dfl: add basic support for DFHv1 matthew.gerlach
2023-01-10 10:21   ` Andy Shevchenko
2023-01-10 22:07     ` matthew.gerlach
2023-01-11  2:13       ` Xu Yilun
2023-01-12 10:27         ` Andy Shevchenko
2023-01-12 15:36           ` matthew.gerlach
2023-01-13  2:22             ` Xu Yilun
2023-01-13 19:05               ` matthew.gerlach
2023-01-12 15:30         ` matthew.gerlach
2023-01-10  0:30 ` [PATCH v10 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2023-01-10 10:32   ` Andy Shevchenko [this message]
2023-01-10 22:17     ` matthew.gerlach

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