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From: Lee Jones <lee@kernel.org>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: linux-fpga@vger.kernel.org, Xu Yilun <yilun.xu@intel.com>,
	Wu Hao <hao.wu@intel.com>, Tom Rix <trix@redhat.com>,
	Moritz Fischer <mdf@kernel.org>,
	Matthew Gerlach <matthew.gerlach@linux.intel.com>,
	Russ Weight <russell.h.weight@intel.com>,
	Tianfei zhang <tianfei.zhang@intel.com>,
	Mark Brown <broonie@kernel.org>,
	Marco Pagani <marpagan@redhat.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 06/10] mfd: intel-m10-bmc: Downscope SPI defines & prefix with M10BMC_N3000
Date: Tue, 10 Jan 2023 17:05:25 +0000	[thread overview]
Message-ID: <Y72a1feFIAMyrVpQ@google.com> (raw)
In-Reply-To: <20221226175849.13056-7-ilpo.jarvinen@linux.intel.com>

On Mon, 26 Dec 2022, Ilpo Järvinen wrote:

> Move SPI based board definitions to per interface file from the global
> header. This makes it harder to use them accidently in the
> generic/interface agnostic code. Prefix the defines with M10BMC_N3000
> to make it more obvious these are related to some board type. All
> current non-N3000 board types have the same layout so they'll be
> reused.
> 
> Some bitfield defs are also moved to intel-m10-bmc-core which seems
> more appropriate for them.
> 
> Reviewed-by: Russ Weight <russell.h.weight@intel.com>
> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> ---
>  drivers/mfd/intel-m10-bmc-core.c  | 11 ++++
>  drivers/mfd/intel-m10-bmc-spi.c   | 89 ++++++++++++++++++++++---------
>  include/linux/mfd/intel-m10-bmc.h | 46 ----------------
>  3 files changed, 74 insertions(+), 72 deletions(-)
> 
> diff --git a/drivers/mfd/intel-m10-bmc-core.c b/drivers/mfd/intel-m10-bmc-core.c
> index 51b78b868235..50a4ec758bdb 100644
> --- a/drivers/mfd/intel-m10-bmc-core.c
> +++ b/drivers/mfd/intel-m10-bmc-core.c
> @@ -12,6 +12,17 @@
>  #include <linux/mfd/intel-m10-bmc.h>
>  #include <linux/module.h>
>  
> +/* Register fields of system registers */
> +#define M10BMC_MAC_BYTE4		GENMASK(7, 0)
> +#define M10BMC_MAC_BYTE3		GENMASK(15, 8)
> +#define M10BMC_MAC_BYTE2		GENMASK(23, 16)
> +#define M10BMC_MAC_BYTE1		GENMASK(31, 24)
> +#define M10BMC_MAC_BYTE6		GENMASK(7, 0)
> +#define M10BMC_MAC_BYTE5		GENMASK(15, 8)
> +#define M10BMC_MAC_COUNT		GENMASK(23, 16)
> +#define M10BMC_VER_MAJOR_MSK		GENMASK(23, 16)
> +#define M10BMC_VER_PCB_INFO_MSK		GENMASK(31, 24)
> +
>  static ssize_t bmc_version_show(struct device *dev,
>  				struct device_attribute *attr, char *buf)
>  {
> diff --git a/drivers/mfd/intel-m10-bmc-spi.c b/drivers/mfd/intel-m10-bmc-spi.c
> index e8986154e965..04c83f9c6492 100644
> --- a/drivers/mfd/intel-m10-bmc-spi.c
> +++ b/drivers/mfd/intel-m10-bmc-spi.c
> @@ -13,10 +13,47 @@
>  #include <linux/regmap.h>
>  #include <linux/spi/spi.h>
>  
> +#define M10BMC_N3000_LEGACY_BUILD_VER	0x300468
> +#define M10BMC_N3000_SYS_BASE		0x300800
> +#define M10BMC_N3000_SYS_END		0x300fff
> +#define M10BMC_N3000_FLASH_BASE		0x10000000
> +#define M10BMC_N3000_FLASH_END		0x1fffffff
> +#define M10BMC_N3000_MEM_END		M10BMC_N3000_FLASH_END
> +
> +/* Register offset of system registers */
> +#define NIOS2_FW_VERSION		0x0
> +#define M10BMC_N3000_MAC_LOW		0x10
> +#define M10BMC_N3000_MAC_HIGH		0x14
> +#define M10BMC_N3000_TEST_REG		0x3c
> +#define M10BMC_N3000_BUILD_VER		0x68
> +#define M10BMC_N3000_VER_LEGACY_INVALID	0xffffffff
> +
> +/* Secure update doorbell register, in system register region */
> +#define M10BMC_N3000_DOORBELL		0x400
> +
> +/* Authorization Result register, in system register region */
> +#define M10BMC_N3000_AUTH_RESULT		0x404
> +
> +/* Addresses for security related data in FLASH */
> +#define M10BMC_N3000_BMC_REH_ADDR	0x17ffc004
> +#define M10BMC_N3000_BMC_PROG_ADDR	0x17ffc000
> +#define M10BMC_N3000_BMC_PROG_MAGIC	0x5746
> +
> +#define M10BMC_N3000_SR_REH_ADDR	0x17ffd004
> +#define M10BMC_N3000_SR_PROG_ADDR	0x17ffd000
> +#define M10BMC_N3000_SR_PROG_MAGIC	0x5253
> +
> +#define M10BMC_N3000_PR_REH_ADDR	0x17ffe004
> +#define M10BMC_N3000_PR_PROG_ADDR	0x17ffe000
> +#define M10BMC_N3000_PR_PROG_MAGIC	0x5250

My preference would definitely be to keep these blocks of defines tucked
away inside a header file somewhere.

Premise of the change looks fine, however.

-- 
Lee Jones [李琼斯]

  reply	other threads:[~2023-01-10 17:05 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-26 17:58 [PATCH v5 00/10] intel-m10-bmc: Split BMC to core and SPI parts & add PMCI+N6000 support Ilpo Järvinen
2022-12-26 17:58 ` [PATCH v5 01/10] mfd: intel-m10-bmc: Create m10bmc_platform_info for type specific info Ilpo Järvinen
2023-01-09 17:43   ` Lee Jones
2023-01-09 18:04     ` Ilpo Järvinen
2023-01-10 10:05       ` Lee Jones
2022-12-26 17:58 ` [PATCH v5 02/10] mfd: intel-m10-bmc: Rename the local variables Ilpo Järvinen
2023-01-09 18:07   ` Lee Jones
2023-01-09 18:17     ` Ilpo Järvinen
2023-01-10 10:13       ` Lee Jones
2022-12-26 17:58 ` [PATCH v5 03/10] mfd: intel-m10-bmc: Split into core and spi specific parts Ilpo Järvinen
2023-01-13 14:42   ` Lee Jones
2022-12-26 17:58 ` [PATCH v5 04/10] mfd: intel-m10-bmc: Support multiple CSR register layouts Ilpo Järvinen
2023-01-13 14:44   ` Lee Jones
2022-12-26 17:58 ` [PATCH v5 05/10] fpga: intel-m10-bmc: Rework flash read/write Ilpo Järvinen
2022-12-26 17:58 ` [PATCH v5 06/10] mfd: intel-m10-bmc: Downscope SPI defines & prefix with M10BMC_N3000 Ilpo Järvinen
2023-01-10 17:05   ` Lee Jones [this message]
2022-12-26 17:58 ` [PATCH v5 07/10] fpga: m10bmc-sec: Create helpers for rsu status/progress checks Ilpo Järvinen
2022-12-30  3:16   ` Xu Yilun
2022-12-26 17:58 ` [PATCH v5 08/10] fpga: m10bmc-sec: Differentiate rsu status from doorbell in csr map Ilpo Järvinen
2022-12-30  4:32   ` Xu Yilun
2022-12-30 10:23     ` Ilpo Järvinen
2023-01-03  9:34       ` Xu Yilun
2023-01-03 12:12         ` Ilpo Järvinen
2022-12-26 17:58 ` [PATCH v5 09/10] mfd: intel-m10-bmc: Add PMCI driver Ilpo Järvinen
2023-01-13 14:40   ` Lee Jones
2023-01-13 15:08     ` Ilpo Järvinen
2022-12-26 17:58 ` [PATCH v5 10/10] fpga: m10bmc-sec: Add support for N6000 Ilpo Järvinen
2022-12-30  6:10   ` Xu Yilun

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