* Re: [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding
[not found] <20230103062610.69704-1-uwu@icenowy.me>
@ 2023-01-03 8:34 ` Heiko Stübner
[not found] ` <20230103062610.69704-2-uwu@icenowy.me>
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Heiko Stübner @ 2023-01-03 8:34 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Nathan Chancellor, Icenowy Zheng
Cc: linux-riscv, linux-kernel, Icenowy Zheng, Sergey Matyukevich
Am Dienstag, 3. Januar 2023, 07:26:09 CET schrieb Icenowy Zheng:
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Original was on
https://lore.kernel.org/all/5894419.tdWV9SEqCh@phil/
> ---
> Included when resending:
> - Sergey's Tested-by tag.
>
> arch/riscv/include/asm/errata_list.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> * dcache.cva rs1 (clean, virtual address)
> - * 0000001 00100 rs1 000 00000 0001011
> + * 0000001 00101 rs1 000 00000 0001011
> *
> * dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \
> * 0000000 11001 00000 000 00000 0001011
> */
> #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread[parent not found: <20230103062610.69704-2-uwu@icenowy.me>]
* Re: [PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th.
[not found] ` <20230103062610.69704-2-uwu@icenowy.me>
@ 2023-01-03 8:35 ` Heiko Stübner
2023-01-03 10:18 ` Conor Dooley
0 siblings, 1 reply; 6+ messages in thread
From: Heiko Stübner @ 2023-01-03 8:35 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Nathan Chancellor, Icenowy Zheng
Cc: linux-riscv, linux-kernel, Icenowy Zheng
Am Dienstag, 3. Januar 2023, 07:26:10 CET schrieb Icenowy Zheng:
> T-Head now maintains some specification for their extended instructions
> at [1], in which all instructions are prefixed "th.".
>
> Follow this practice in the kernel comments.
>
> [1] https://github.com/T-head-Semi/thead-extension-spec
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th.
2023-01-03 8:35 ` [PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th Heiko Stübner
@ 2023-01-03 10:18 ` Conor Dooley
2023-01-03 19:10 ` Conor Dooley
0 siblings, 1 reply; 6+ messages in thread
From: Conor Dooley @ 2023-01-03 10:18 UTC (permalink / raw)
To: Heiko Stübner, uwu
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Nathan Chancellor, Icenowy Zheng, linux-riscv, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 779 bytes --]
> T-Head now maintains some specification for their extended instructions
> at [1], in which all instructions are prefixed "th.".
>
> Follow this practice in the kernel comments.
>
> [1] https://github.com/T-head-Semi/thead-extension-spec
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Hey Icenowy,
This (yet again) appears to not have made it to the list.
It's not on patchwork, nor lore:
https://lore.kernel.org/linux-riscv/2668919.mvXUDI8C0e@diego/T/#t
https://lore.kernel.org/all/2668919.mvXUDI8C0e@diego/T/#t
Since you CCed lkml & not just linux-riscv, but it is not showing idk
what's wrong..
Your reply to me the other day came through:
https://lore.kernel.org/all/dda144a8397a175f3ce092485f08896c9a66d232.camel@icenowy.me/
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th.
2023-01-03 10:18 ` Conor Dooley
@ 2023-01-03 19:10 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2023-01-03 19:10 UTC (permalink / raw)
To: Heiko Stübner, uwu
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Nathan Chancellor, linux-riscv, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1138 bytes --]
On Tue, Jan 03, 2023 at 10:18:49AM +0000, Conor Dooley wrote:
> > T-Head now maintains some specification for their extended instructions
> > at [1], in which all instructions are prefixed "th.".
> >
> > Follow this practice in the kernel comments.
> >
> > [1] https://github.com/T-head-Semi/thead-extension-spec
> >
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
>
> Hey Icenowy,
> This (yet again) appears to not have made it to the list.
> It's not on patchwork, nor lore:
> https://lore.kernel.org/linux-riscv/2668919.mvXUDI8C0e@diego/T/#t
> https://lore.kernel.org/all/2668919.mvXUDI8C0e@diego/T/#t
>
> Since you CCed lkml & not just linux-riscv, but it is not showing idk
> what's wrong..
> Your reply to me the other day came through:
> https://lore.kernel.org/all/dda144a8397a175f3ce092485f08896c9a66d232.camel@icenowy.me/
This (and the previous iteration) finally came through to the list.
I guess the pusher-of-buttons for "suspicious" mail or w/e is back to
work after Christmas. It's in patchwork now:
https://patchwork.kernel.org/project/linux-riscv/list/?series=708586
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding
[not found] <20230103062610.69704-1-uwu@icenowy.me>
2023-01-03 8:34 ` [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding Heiko Stübner
[not found] ` <20230103062610.69704-2-uwu@icenowy.me>
@ 2023-01-03 12:02 ` Guo Ren
2023-01-24 13:19 ` Icenowy Zheng
3 siblings, 0 replies; 6+ messages in thread
From: Guo Ren @ 2023-01-03 12:02 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Heiko Stuebner,
Nathan Chancellor, linux-riscv, linux-kernel, Sergey Matyukevich
Reviewed-by: Guo Ren <guoren@kernel.org>
On Tue, Jan 3, 2023 at 2:26 PM Icenowy Zheng <uwu@icenowy.me> wrote:
>
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> ---
> Included when resending:
> - Sergey's Tested-by tag.
>
> arch/riscv/include/asm/errata_list.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> * dcache.cva rs1 (clean, virtual address)
> - * 0000001 00100 rs1 000 00000 0001011
> + * 0000001 00101 rs1 000 00000 0001011
> *
> * dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \
> * 0000000 11001 00000 000 00000 0001011
> */
> #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
> --
> 2.38.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding
[not found] <20230103062610.69704-1-uwu@icenowy.me>
` (2 preceding siblings ...)
2023-01-03 12:02 ` [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding Guo Ren
@ 2023-01-24 13:19 ` Icenowy Zheng
3 siblings, 0 replies; 6+ messages in thread
From: Icenowy Zheng @ 2023-01-24 13:19 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Heiko Stuebner, Guo Ren,
Nathan Chancellor
Cc: linux-riscv, linux-kernel, Sergey Matyukevich
在 2023-01-03星期二的 14:26 +0800，Icenowy Zheng写道：
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Could this patch be included?
As I know, at least two C910 SoCs will be generally available, T-Head's
own TH1520 and Sophgo SG2042.
> ---
> Included when resending:
> - Sergey's Tested-by tag.
>
> arch/riscv/include/asm/errata_list.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h
> b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm
> volatile(ALTERNATIVE( \
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> * dcache.cva rs1 (clean, virtual address)
> - * 0000001 00100 rs1 000 00000 0001011
> + * 0000001 00101 rs1 000 00000 0001011
> *
> * dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm
> volatile(ALTERNATIVE( \
> * 0000000 11001 00000 000 00000 0001011
> */
> #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
^ permalink raw reply [flat|nested] 6+ messages in thread