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[31.46.243.128]) by smtp.gmail.com with ESMTPSA id r4-20020a17090638c400b007c16f120aacsm16191561ejd.121.2023.01.05.02.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 02:03:41 -0800 (PST) Sender: Ingo Molnar Date: Thu, 5 Jan 2023 11:03:37 +0100 From: Ingo Molnar To: Guo Ren Cc: Waiman Long , peterz@infradead.org, linux-kernel@vger.kernel.org, Guo Ren , Boqun Feng , Will Deacon , Ingo Molnar Subject: Re: [PATCH] locking/qspinlock: Optimize pending state waiting for unlock Message-ID: References: <20221224120545.262989-1-guoren@kernel.org> <08ce1ab6-4678-74ce-43cc-2d3f04d1525d@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Guo Ren wrote: > On Thu, Jan 5, 2023 at 4:19 AM Ingo Molnar wrote: > > > > > > * Guo Ren wrote: > > > > > > >> The situation is the SMT scenarios in the same core. Not an entering > > > > >> low-power state situation. Of course, the granularity between cores is > > > > >> "cacheline", but the granularity between SMT hw threads of the same > > > > >> core could be "byte" which internal LSU handles. For example, when a > > > > >> hw-thread yields the resources of the core to other hw-threads, this > > > > >> patch could help the hw-thread stay in the sleep state and prevent it > > > > >> from being woken up by other hw-threads xchg_tail. > > > > >> > > > > >> Finally, from the software semantic view, does the patch make it more > > > > >> accurate? (We don't care about the tail here.) > > > > > > > > > > Thanks for the clarification. > > > > > > > > > > I am not arguing for the simplification part. I just want to clarify > > > > > my limited understanding of how the CPU hardware are actually dealing > > > > > with these conditions. > > > > > > > > > > With that, I am fine with this patch. It would be nice if you can > > > > > elaborate a bit more in your commit log. > > > > > > > > > > Acked-by: Waiman Long > > > > > > > > > BTW, have you actually observe any performance improvement with this patch? > > > Not yet. I'm researching how the hardware could satisfy qspinlock > > > better. Here are three points I concluded: > > > 1. Atomic forward progress guarantee: Prevent unnecessary LL/SC > > > retry, which may cause expensive bus transactions when crossing the > > > NUMA nodes. > > > 2. Sub-word atomic primitive: Enable freedom from interference > > > between locked, pending, and tail. > > > 3. Load-cond primitive: Prevent processor from wasting loop > > > operations for detection. > > > > As to this patch, please send a -v2 version of this patch that has this > > discussion & explanation included in the changelog, as requested by Waiman. > Done > > https://lore.kernel.org/lkml/20230105021952.3090070-1-guoren@kernel.org/ Applied to tip:locking/core for a v6.3 merge, thanks! Ingo