Re: [PATCH 10/16] spi: bcm63xx-hsspi: Make dummy cs workaround as an option

[Mark Brown <broonie@kernel.org>]

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On Fri, Jan 06, 2023 at 12:08:02PM -0800, William Zhang wrote:

> Due to the controller limitation to keep the chip select low during the
> bus idle time between the transfer, a dummy cs workaround was used when
> this driver was first upstreamed to the kernel.
> 
> The workaround picks dummy_cs as !actual_cs and usually cs is 0 and
> dummy cs is 1. But this does not work out in all the situations as
> customer reported issues for their board design. Due to SPI block design
> constrain, the controller works in different mode internally depending
> on the clock. When clock is 30MHz or above, controller works in faster
> mode and cs 1 signal is used internally as feedback from the pad. So cs
> 1 pin must be brought out and configured as chip select function in
> pinmux. When clock is below 30MHz, only cs 0 pin is used. In summary
> when clock is below 30MHz, the workaround always works as only cs 0 is
> involved. For clock faster than 30MHz, it require cs1 pin used in the
> board design and configured as chip selection function.

> In a typical usage of SPI flash on cs 0 that normally runs at 100MHz,
> cs 1 pin must be used in the board design but this is not always the
> case for many customer boards.

> For voice daughtercard usage,  the SoC alway uses internal cs 7 for
> voice card SPI control. Then it requires cs 0 pin as the dummy cs but
> board with voice design may not use cs 0 pin at all.

So I think what this is trying to say is that operation over 30MHz with
the existing workaround requires that the board be designed to bring out
the chip select used as the dummy as a physical chip select (or
potentially it has to be the actual chip select for the device?) but
that likely won't have been done?  And potentially this only works if CS
1 is the one brought out?  I'm unclear if CS 1 is just the most common
dummy chip select or if there's something else going on here.

> The controller actually has a prepend feature that can combine multiple
> SPI transfers in a SPI message into one single transfer when the
> transfers meet certain requirements. So there is no need for keeping cs
> low when the message only has one transfer. Most of the SPI devices
> including SPI NOR, SPI NAND flash, Broadcom voice card and etc can use
> this feature without the dummy cs workaround.

> This patch makes the dummy cs workaround as an option based on the
> dts flag brcm,use-cs-workaround. By default dummy cs workaround is
> hard coded to enable. We will use the prepend feature and disable this
> workaround as default in the next patch of this series unless this flag
> is set in dts.

...and based on your other comments I gather it's difficult to disable
the workaround per message?  I'm also guessing that the overhead from
always doing full duplex transfers is noticable so it's better to try
the workaround.

I wonder if we can't do this by selecting the workaround based on the
configured device speed.  If the device is configured to use more than
30MHz then disable the workaround, if it's set to lower then use it.  In
practice most devices don't change their speed after setup, and the
driver could check for and handle that case I guess (eg, limit the speed
configured if the workaround has been activated or rewrite the message
to a single transfer if neded).  That would be less error prone for
users, there wouldn't be any possibility of them setting this flag
incorrectly.

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