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[2003:e4:1f20:1d00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id tc9-20020a1709078d0900b0086edf177209sm2343403ejc.78.2023.01.16.08.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 08:29:05 -0800 (PST) Date: Mon, 16 Jan 2023 17:29:02 +0100 From: Thierry Reding To: Sumit Gupta Cc: treding@nvidia.com, krzysztof.kozlowski@linaro.org, dmitry.osipenko@collabora.com, viresh.kumar@linaro.org, rafael@kernel.org, jonathanh@nvidia.com, robh+dt@kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, sanjayc@nvidia.com, ksitaraman@nvidia.com, ishah@nvidia.com, bbasu@nvidia.com Subject: Re: [Patch v1 06/10] arm64: tegra: Add cpu OPP tables and interconnects property Message-ID: References: <20221220160240.27494-1-sumitg@nvidia.com> <20221220160240.27494-7-sumitg@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ZMip0bUSH42JeHsT" Content-Disposition: inline In-Reply-To: <20221220160240.27494-7-sumitg@nvidia.com> User-Agent: Mutt/2.2.9 (2022-11-12) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --ZMip0bUSH42JeHsT Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Dec 20, 2022 at 09:32:36PM +0530, Sumit Gupta wrote: > Add OPP table and interconnects property required to scale DDR > frequency for better performance. The OPP table has CPU frequency > to per MC channel bandwidth mapping in each operating point entry. > One table is added for each cluster even though the table data is > same because the bandwidth request is per cluster. OPP framework > is creating a single icc path if the table is marked 'opp-shared' > and shared among all clusters. For us the OPP table is same but > the MC client ID argument to interconnects property is different > for each cluster which makes different icc path for all. >=20 > Signed-off-by: Sumit Gupta > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 276 +++++++++++++++++++++++ > 1 file changed, 276 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/d= ts/nvidia/tegra234.dtsi > index eaf05ee9acd1..ed7d0f7da431 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > @@ -2840,6 +2840,9 @@ > =20 > enable-method =3D "psci"; > =20 > + operating-points-v2 =3D <&cl0_opp_tbl>; > + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; I dislike how this muddies the water between hardware and software description. We don't have a hardware client ID for the CPU clusters, so there's no good way to describe this in a hardware-centric way. We used to have MPCORE read and write clients for this, but as far as I know they used to be for the entire CCPLEX rather than per-cluster. It'd be interesting to know what the BPMP does underneath, perhaps that could give some indication as to what would be a better hardware value to use for this. Failing that, I wonder if a combination of icc_node_create() and icc_get() can be used for this type of "virtual node" special case. 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