From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEFCDC54EBE for ; Mon, 16 Jan 2023 18:11:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232448AbjAPSLO (ORCPT ); Mon, 16 Jan 2023 13:11:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234620AbjAPSKZ (ORCPT ); Mon, 16 Jan 2023 13:10:25 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBC6E40BDB; Mon, 16 Jan 2023 09:55:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673891709; x=1705427709; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=nPJ0Oql8v3SfaPq35P3fWDHJnWjk2fijB0EmpflPsqw=; b=T/7TnbW9cHEY4M5nwmUlxgrKhEbRx+wicjzdKw6V7f4X/KuAmu8imczQ MrKry9eYx/ag3Ek7stmLCUiGYv+ke1VfKe4KVeCdLf4ya2kctAIJl8vXj 6PajTuB+BIxMK/9xnMe/CD/qzE1aWHlj7zrjxATa0h3QYAXkE7nsI5tl2 LeawyRuQy7IJDim7nzjKpW+ySJ0XQtw+aseNJCLFyH3TUxlkKr3pVJsHb JEwLzKX0XGYtuKbhdFyhRFC23/nBtJlNuOrFlISZdxARez6mRKSD6d6Rq 2QeR2lqmZFHNFQuiDIjtHNudWFgG2ZehovIIetlZJ0fR1x6lo9aP/EgqX g==; X-IronPort-AV: E=McAfee;i="6500,9779,10592"; a="304896132" X-IronPort-AV: E=Sophos;i="5.97,221,1669104000"; d="scan'208";a="304896132" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2023 09:54:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10592"; a="987873528" X-IronPort-AV: E=Sophos;i="5.97,221,1669104000"; d="scan'208";a="987873528" Received: from smile.fi.intel.com ([10.237.72.54]) by fmsmga005.fm.intel.com with ESMTP; 16 Jan 2023 09:54:29 -0800 Received: from andy by smile.fi.intel.com with local (Exim 4.96) (envelope-from ) id 1pHTgh-00ACjM-2z; Mon, 16 Jan 2023 19:54:27 +0200 Date: Mon, 16 Jan 2023 19:54:27 +0200 From: Andy Shevchenko To: "Limonciello, Mario" Cc: Jan =?utf-8?B?RMSFYnJvxZs=?= , Borislav Petkov , Borislav Petkov , Hans de Goede , "linux-kernel@vger.kernel.org" , "linux-i2c@vger.kernel.org" , "jarkko.nikula@linux.intel.com" , "wsa@kernel.org" , "rrangel@chromium.org" , "upstream@semihalf.com" , "M K, Muralidhara" , "Chatradhi, Naveen Krishna" , "Ghannam, Yazen" Subject: Re: [PATCH -next 1/2] i2c: designware: Switch from using MMIO access to SMN access Message-ID: References: <33d5cc27-474b-fdec-a6b0-84ac16f7d386@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 16, 2023 at 07:48:10PM +0200, Andy Shevchenko wrote: > On Mon, Jan 16, 2023 at 04:22:09PM +0000, Limonciello, Mario wrote: > > > From: Andy Shevchenko > > > Sent: Monday, January 16, 2023 06:39 > > > To: Jan Dąbroś > > > On Mon, Jan 16, 2023 at 11:19:00AM +0100, Jan Dąbroś wrote: > > > > > > Make init_amd_nbs() arch_initcall_sync() so that it executes after PCI > > > init. > > > > > > > > I described earlier in this thread why such option is not working - > > > > let me quote myself: > > > > > > > > It's not enough for running init_amd_nbs() to have only > > > > pci_arch_init() done. We need the pci bus to be created and registered > > > > with all devices found on the bus. We are traversing through them and > > > > trying to find northbridge VID/DID. Due to the above, we need to run > > > > init_amd_nbs() only after acpi_scan_init() that is invoked from > > > > acpi_init() which is registered as subsys_initcall. That's why the > > > > trick with switching init_amd_nbs() to arch_initcall_sync will not > > > > work. > > > > > > > > We have a kind of chicken-and-egg problem here. Or is there something I > > > missed? > > > > > > > > I wonder if there is upstreamable option to control order of the > > > > drivers' init by forcing link order? > > > > > > But what exactly do you need from North Bridge? Is it only its existence or > > > do you need to have fully instantiated PCI device (if so, why?)? > > > > There is a need to be able to write and read PCI config space. > > So, it's available even on early stages, are there some specifics why it can't > be done using the respective APIs? I think I understood the problem with the above. You probably don't know where NB can be located in the topology and that's why you can't simply access a _fixed_ BDF. So you want to have the topology being scanned beforehand. -- With Best Regards, Andy Shevchenko