[tip: perf/urgent] perf/x86/msr: Add Emerald Rapids

tip-bot2 for Kan Liang
2023-01-09T11:15:46Z

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID: 69ced4160969025821f2999ff92163ed26568f1c
Gitweb: https://git.kernel.org/tip/69ced4160969025821f2999ff92163ed26568f1c
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Fri, 06 Jan 2023 08:04:48 -08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Mon, 09 Jan 2023 12:00:52 +01:00

perf/x86/msr: Add Emerald Rapids

The same as Sapphire Rapids, the SMI_COUNT MSR is also supported on
Emerald Rapids. Add Emerald Rapids model.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230106160449.3566477-3-kan.liang@linux.intel.com
---
arch/x86/events/msr.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 074150d..c65d890 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -69,6 +69,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_BROADWELL_G:
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SAPPHIRERAPIDS_X:
+ case INTEL_FAM6_EMERALDRAPIDS_X:

case INTEL_FAM6_ATOM_SILVERMONT:
case INTEL_FAM6_ATOM_SILVERMONT_D: