From: Conor Dooley <conor@kernel.org>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, leyfoon.tan@starfivetech.com,
mason.huo@starfivetech.com
Subject: Re: [PATCH v3 2/4] RISC-V: Factor out common code of __cpu_resume_enter()
Date: Mon, 30 Jan 2023 21:49:17 +0000 [thread overview]
Message-ID: <Y9g7XeTbWjCxB3BT@spud> (raw)
In-Reply-To: <20230127091051.1465278-3-jeeheng.sia@starfivetech.com>
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On Fri, Jan 27, 2023 at 05:10:49PM +0800, Sia Jee Heng wrote:
> The cpu_resume() function is very similar for the suspend to disk and
> suspend to ram cases. Factor out the common code into restore_csr macro
> and restore_reg macro.
>
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> ---
> arch/riscv/include/asm/assembler.h | 62 ++++++++++++++++++++++++++++++
> arch/riscv/kernel/suspend_entry.S | 34 ++--------------
> 2 files changed, 65 insertions(+), 31 deletions(-)
> create mode 100644 arch/riscv/include/asm/assembler.h
>
> diff --git a/arch/riscv/include/asm/assembler.h b/arch/riscv/include/asm/assembler.h
> new file mode 100644
> index 000000000000..ef1283d04b70
> --- /dev/null
> +++ b/arch/riscv/include/asm/assembler.h
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + *
> + * Author: Jee Heng Sia <jeeheng.sia@starfivetech.com>
> + */
> +
> +#ifndef __ASSEMBLY__
> +#error "Only include this from assembly code"
> +#endif
> +
> +#ifndef __ASM_ASSEMBLER_H
> +#define __ASM_ASSEMBLER_H
> +
> +#include <asm/asm.h>
> +#include <asm/csr.h>
> +#include <asm/asm-offsets.h>
> +
> +/**
> + * restore_csr - restore hart's CSR value
> + */
> + .macro restore_csr
> + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
> + csrw CSR_EPC, t0
> + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
> + csrw CSR_STATUS, t0
> + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
> + csrw CSR_TVAL, t0
> + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
> + csrw CSR_CAUSE, t0
> + .endm
> +
> +/**
> + * restore_reg - Restore registers (except A0 and T0-T6)
arch/riscv/include/asm/assembler.h:34: warning: Incorrect use of kernel-doc format: * restore_reg - Restore registers (except A0 and T0-T6)
Otherwise, LGTM.
> + */
> + .macro restore_reg
> + REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
> + REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
> + REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
> + REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
> + REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
> + REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
> + REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
> + REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
> + REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
> + REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
> + REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
> + REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
> + REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
> + REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
> + REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
> + REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
> + REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
> + REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
> + REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
> + REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
> + REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
> + REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
> + REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
> + .endm
> +
> +#endif /* __ASM_ASSEMBLER_H */
> diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S
> index aafcca58c19d..74a8fab8e0f6 100644
> --- a/arch/riscv/kernel/suspend_entry.S
> +++ b/arch/riscv/kernel/suspend_entry.S
> @@ -7,6 +7,7 @@
> #include <linux/linkage.h>
> #include <asm/asm.h>
> #include <asm/asm-offsets.h>
> +#include <asm/assembler.h>
> #include <asm/csr.h>
> #include <asm/xip_fixup.h>
>
> @@ -83,39 +84,10 @@ ENTRY(__cpu_resume_enter)
> add a0, a1, zero
>
> /* Restore CSRs */
> - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
> - csrw CSR_EPC, t0
> - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
> - csrw CSR_STATUS, t0
> - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
> - csrw CSR_TVAL, t0
> - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
> - csrw CSR_CAUSE, t0
> + restore_csr
>
> /* Restore registers (except A0 and T0-T6) */
> - REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
> - REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
> - REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
> - REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
> - REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
> - REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
> - REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
> - REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
> - REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
> - REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
> - REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
> - REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
> - REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
> - REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
> - REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
> - REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
> - REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
> - REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
> - REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
> - REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
> - REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
> - REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
> - REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
> + restore_reg
>
> /* Return zero value */
> add a0, zero, zero
> --
> 2.34.1
>
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next prev parent reply other threads:[~2023-01-30 21:49 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-27 9:10 [PATCH v3 0/4] RISC-V Hibernation Support Sia Jee Heng
2023-01-27 9:10 ` [PATCH v3 1/4] RISC-V: Change suspend_save_csrs and suspend_restore_csrs to public function Sia Jee Heng
2023-01-30 23:31 ` Conor Dooley
2023-01-27 9:10 ` [PATCH v3 2/4] RISC-V: Factor out common code of __cpu_resume_enter() Sia Jee Heng
2023-01-30 21:49 ` Conor Dooley [this message]
2023-02-01 6:19 ` JeeHeng Sia
2023-01-27 9:10 ` [PATCH v3 3/4] RISC-V: mm: Enable huge page support to kernel_page_present() function Sia Jee Heng
2023-01-30 21:57 ` Conor Dooley
2023-01-31 8:19 ` Alexandre Ghiti
2023-02-01 5:48 ` JeeHeng Sia
2023-01-27 9:10 ` [PATCH v3 4/4] RISC-V: Add arch functions to support hibernation/suspend-to-disk Sia Jee Heng
2023-01-30 23:30 ` Conor Dooley
2023-01-31 9:59 ` Alexandre Ghiti
2023-02-07 4:58 ` JeeHeng Sia
2023-02-07 5:27 ` Alexandre Ghiti
2023-02-02 2:43 ` JeeHeng Sia
2023-02-03 3:43 ` JeeHeng Sia
2023-02-03 6:30 ` Conor Dooley
2023-02-04 20:42 ` kernel test robot
2023-02-07 15:46 ` Alexandre Ghiti
2023-02-08 4:43 ` JeeHeng Sia
2023-02-08 12:04 ` Alexandre Ghiti
2023-02-09 6:12 ` JeeHeng Sia
2023-02-10 13:24 ` Alexandre Ghiti
2023-02-13 1:51 ` JeeHeng Sia
2023-02-14 6:57 ` Alexandre Ghiti
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