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Date:   Mon, 25 Jan 2021 15:23:46 +0100
From:   gregkh <gregkh@linuxfoundation.org>
To:     Paul Cercueil <paul@crapouillou.net>
Cc:     Linus Walleij <linus.walleij@linaro.org>,
        stable <stable@vger.kernel.org>, linux-gpio@vger.kernel.org,
        linux-kernel@vger.kernel.org, od@zcrc.me
Subject: Re: [BACKPORT 5.4 PATCH] pinctrl: ingenic: Fix JZ4760 support
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 <20210124134704.202931-1-paul@crapouillou.net>
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On Sun, Jan 24, 2021 at 01:49:32PM +0000, Paul Cercueil wrote:
> 
> 
> Le dim. 24 janv. 2021 à 13:47, Paul Cercueil <paul@crapouillou.net> a écrit
> :
> > - JZ4760 and JZ4760B have a similar register layout as the JZ4740, and
> >   don't use the new register layout, which was introduced with the
> >   JZ4770 SoC and not the JZ4760 or JZ4760B SoCs.
> > 
> > - The JZ4740 code path only expected two function modes to be
> >   configurable for each pin, and wouldn't work with more than two. Fix
> >   it for the JZ4760, which has four configurable function modes.
> 
> Forgot to add the original commit ID:
> 9a85c09a3f507b925d75cb0c7c8f364467038052

Thanks, now queued up.

greg k-h